MPC8572EPXAVNB datasheet(81/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 53. Single-Ended Measurement Points for Rise and Fall Time Matching

The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol

based on application usage. Refer to the following sections for detailed information:

•

Section 8.3.2, “AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK”

•

Section 16.2, “AC Requirements for PCI Express SerDes Reference Clocks”

•

Section 17.2, “AC Requirements for Serial RapidIO SD1_REF_CLK and SD1_REF_CLK”

15.2.4.1

Spread Spectrum Clock

SD1_REF_CLK/SD1_REF_CLK are designed to work with a spread spectrum clock (+0 to –0.5%

spreading at 30–33 KHz rate is allowed), assuming both ends have same reference clock. For better results,

a source without significant unintended modulation should be used.

SD2_REF_CLK/SD2_REF_CLK are not to be used with, and should not be clocked by, a spread spectrum

clock source.

15.3

SerDes Transmitter and Receiver Reference Circuits

Figure 54 shows the reference circuits for SerDes data lane’s transmitter and receiver.

Figure 54. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below

(PCI Express, Serial Rapid IO or SGMII) in this document based on the application usage:

•

Section 8.3, “SGMII Interface Electrical Characteristics”

n_REF_CLK

Receiver

Transmitter

SD1_TX

n or

SD2_TX

SD1_TX

n or

SD2_TX

SD1_RX

n or

SD2_RX

SD1_RX

n or

SD2_RX

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