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MPC8572ECPXATLB 数据表(PDF) 21 Page - Freescale Semiconductor, Inc |
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MPC8572ECPXATLB 数据表(HTML) 21 Page - Freescale Semiconductor, Inc |
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21 / 140 page  MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 21 DDR2 and DDR3 SDRAM Controller AC specifications of the DDR3 memory to be used are compliant to both JEDEC specifications as well as the specifications and requirements described in this MPC8572E hardware specifications document. 6.2.1 DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications Table 14, Table 15, and Table 16 provide the input AC timing specifications for the DDR controller when interfacing to DDR2 and DDR3 SDRAM. Table 14. DDR2 SDRAM Interface Input AC Timing Specifications for 1.8-V Interface At recommended operating conditions with GVDD of 1.8 V ± 5% Parameter Symbol Min Max Unit Notes AC input low voltage >=667 MHz VILAC —MVREFn – 0.20 V — <= 533 MHz — MVREFn – 0.25 AC input high voltage >=667 MHz VIHAC MVREFn + 0.20 — V — — <= 533 MHz MVREFn + 0.25 — Table 15. DDR3 SDRAM Interface Input AC Timing Specifications for 1.5-V Interface At recommended operating conditions with GVDD of 1.5 V ± 5%. DDR3 data rate is between 606 MHz and 800 MHz. Parameter Symbol Min Max Unit Notes AC input low voltage VILAC —MVREFn – 0.175 V — AC input high voltage VIHAC MVREFn + 0.175 — V — Table 16. DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3. Parameter Symbol Min Max Unit Notes Controller Skew for MDQS—MDQ/MECC tCISKEW — — ps 1, 2 800 MHz — –200 200 — — 667 MHz — –240 240 — — 533 MHz — –300 300 — — 400 MHz — –365 365 — — Note: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is captured with MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be determined by the following equation: tDISKEW =+/–(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. |
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