MPC8572ECPXARLB datasheet(3/140 Pages) FREESCALE

3 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Overview

– Four inbound windows plus a default window on serial RapidIO™

– Four outbound windows plus default translation for PCI Express

– Eight outbound windows plus default translation for serial RapidIO with segmentation and

sub-segmentation support

•

Two 64-bit DDR2/DDR3 memory controllers

— Programmable timing supporting DDR2 and DDR3 SDRAM

— 64-bit data interface per controller

— Four banks of memory supported, each up to 4 Gbytes, for a maximum of 16 Gbytes per

controller

— DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports

— Full ECC support

— Page mode support

– Up to 32 simultaneous open pages for DDR2 or DDR3

— Contiguous or discontiguous memory mapping

— Cache line, page, bank, and super-bank interleaving between memory controllers

— Read-modify-write support for RapidIO atomic increment, decrement, set, and clear

transactions

— Sleep mode support for self-refresh SDRAM

— On-die termination support when using DDR2 or DDR3

— Supports auto refreshing

— On-the-fly power management using CKE signal

— Registered DIMM support

— Fast memory access through JTAG port

— 1.8-V SSTL_1.8 compatible I/O

— Support 1.5-V operation for DDR3. The detail is TBD pending on official release of

appropriate industry specifications.

— Support for battery-backed main memory

•

Programmable interrupt controller (PIC)

— Programming model is compliant with the OpenPIC architecture.

— Supports 16 programmable interrupt and processor task priority levels

— Supports 12 discrete external interrupts

— Supports 4 message interrupts per processor with 32-bit messages

— Supports connection of an external interrupt controller such as the 8259 programmable

interrupt controller

— Four global high resolution timers/counters per processor that can generate interrupts

— Supports a variety of other internal interrupt sources

— Supports fully nested interrupt delivery

— Interrupts can be routed to external pin for external processing.

MPC8572ECPXARLB 数据表(PDF) 3 Page - Freescale Semiconductor, Inc

MPC8572ECPXARLB 数据表(HTML) 3 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载