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MMA6900K 数据表(PDF) 13 Page - Freescale Semiconductor, Inc |
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MMA6900K 数据表(HTML) 13 Page - Freescale Semiconductor, Inc |
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13 / 36 page ![]() Sensors Freescale Semiconductor 13 MMA690xQ Figure 2-4 Voltage Monitoring 2.3 OSCILLATOR An internal oscillator operating at a nominal frequency of 4.0 MHz provides a stable clock source. The oscillator is factory trimmed for best performance. A clock generator block divides the 4.0 MHz clock as needed by other blocks. 2.4 CREG MONITOR A monitor circuit is incorporated to ensure predictable operation of the device in the event that the connection to the external capacitor at the CREG pin (pin 8) fails, or the capacitor opens. The monitor disables the 2.5 V regulator which powers the digital circuitry for 2.0 μs every 249.5 μs. If the external capacitor is not present, voltage at the internal supply rail will drop below the internal reset threshold, continuously forcing the device into reset. Loss of communication from the device is a readily detectable condition. The XOUT and YOUT pins are driven to the low rail when the device is in the reset state. 2.5 CLOCK MONITOR Two independent oscillators are provided within MMA690xQ. One is factory-trimmed and provides the timing reference used throughout the device. The second oscillator acts as a reference for the first. If the frequency of these two oscillators varies by more than 10%, an oscillator fault condition is determined. In normal operating mode, an oscillator fault will cause the DOUT pin to be forced to a continuous logic high state when CS is asserted, as described in Section 3.1.1.2. POR VCC VREGA VBG VREG VREF VBGA REFER TO SECTION 5.3 FOR POWER-ON RESET THRESHOLD LIMITS. + - + - + - + - VOLTAGE DIVIDER VOLTAGE DIVIDER VOLTAGE DIVIDER VOLTAGE DIVIDER + - VOLTAGE DIVIDER + - VOLTAGE DIVIDER OV UV UV UV OV OV + - VOLTAGE DIVIDER UV |
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