24

AVR32768

32157A-AVR-12/10

14 JTAG and Nexus debug ports

14.1 JTAG port interface

Figure 14-1.

JTAG port interface example schematic.

TCK

TDO

TMS

RESET

TDI

100 nF

VDD

EVTO

7

8

TDO

3

VCC

4

TMS

5

RESET

6

TDI

9

GND

10

TCK

1

GND

2

2 x 5

header

Table 14-1.

JTAG port interface checklist.

Signal name

Recommended pin connection

Description

TMS

Test mode select, sampled on rising TCK

TDO

Test data output, driven on falling TCK

TCK

Test clock, fully asynchronous to system clock frequency

RESET

Device external reset line

TDI

Test data input, sampled on rising TCK

EVTO

Event output, not used

14.2 Nexus port interface

Do not use any capacitors on NEXUS lines because they can cause a speed

limitation. NEXUS uses GPIO multiplexed lines, and these should be dedicated for

NEXUS when used.