ADP5587

Rev. B | Page 19 of 24

Table 27. GPIO_INT_ENx—Register 0x1A to Register 0x1C (GPIO Interrupt Enable)

Register Name

Register Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GPIO_INT_EN1

(Register 0x1A)

GPIO interrupt enable (enables interrupts for

GP inputs only)

R7IE

R6IE

R5IE

R4IE

R3IE

R2IE

R1IE

R0IE

GPIO_INT_EN2

(Register 0x1B)

GPIO interrupt enable (enables interrupts for

GP inputs only)

C7IE

C6IE

C5IE

C4IE

C3IE

C2IE

C1IE

C0IE

GPIO_INT_EN3

(Register 0x1C)

GPIO interrupt enable (enables interrupts for

GP inputs only)

N/A

N/A

N/A

N/A

N/A

N/A

C9IE

C8IE

Table 28. KP_GPIOx—Register 0x1D to Register 0x1F (Keypad or GPIO Selection)

Register Name

Register Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

KP_GPIO1

(Register 0x1D)

Keypad or GPIO selection

0: GPIO

1: KP matrix

R7

R6

R5

R4

R3

R2

R1

R0

KP_GPIO2

(Register 0x1E)

Keypad or GPIO selection

0: GPIO

1: KP matrix

C7

C6

C5

C4

C3

C2

C1

C0

KP_GPIO3

(Register 0x1F)

Keypad or GPIO selection

0: GPIO

1: KP matrix

N/A

N/A

N/A

N/A

N/A

N/A

C9

C8

Table 29. GPI_EM_REGx—Register 0x20 to Register 0x22 (GPI Event Mode 1 to GPI Event Mode 3)

Register Name

Register Description

Bit 7

Bit 6

Bit

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GPI_EM_REG1

(Register 0x20)

GPI Event Mode Register 1

0: GPI not part of event FIFO

1: GPI part of event FIFO (R0 to R7)

R7_EM

R6_EM

R5_EM

R4_EM

R3_EM

R2_EM

R1_EM

R0_EM

GPI_EM_REG2

(Register 0x21)

GPI Event Mode Register 2

0: GPI not part of event FIFO

1: GPI part of event FIFO (C0 to C7)

C7_EM

C6_EM

C5_EM

C4_EM

C3_EM

C2_EM

C1_EM

C0_EM

GPI_EM_REG3

(Register 0x22)

GPI Event Mode Register 3

0: GPI not part of event FIFO

1: GPI part of event FIFO (C8 to C9)

NA

NA

NA

NA

NA

NA

C9_EM

C8_EM

Table 30. GPIO_DIRx—Register 0x23 to Register 0x25 (GPIO Data Direction)

Register Name

Register Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GPIO_DIR1

(Register 0x23)

GPIO data direction

0: input

1: output

R7D

R6D

R5D

R4D

R3D

R2D

R1D

R0D

GPIO_DIR2

(Register 0x24)

GPIO data direction

0: input

1: output

C7D

C6D

C5D

C4D

C3D

C2D

C1D

C0D

GPIO_DIR3

(Register 0x25)

GPIO data direction

0: input

1: output

N/A

N/A

N/A

N/A

N/A

N/A

C9D

C8D

Table 31. GPIO_INT_LVLx—Register 0x26 to Register 0x28 (GPIO Level Detect)

Register Name

Register Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GPIO_INT_LVL1

(Register 0x26)

GPIO INT level detect

0: low

1: high

R7IL

R6IL

R5IL

R4IL

R3IL

R2IL

R1IL

R0IL

GPIO_INT_LVL2

(Register 0x27)

GPIO INT level detect

0: low

1: high

C7IL

C6IL

C5IL

C4IL

C3IL

C2IL

C1IL

C0IL

GPIO_INT_LVL3

(Register 0x28)

GPIO INT level detect

0: low

1: high

N/A

N/A

N/A

N/A

N/A

N/A

C9IL

C8IL