M41T66

Clock operation

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Clock operation

The M41T66 is driven by a quartz-controlled oscillator with a nominal frequency of

32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz

crystal that is used as the time-base for the RTC.

The eight byte clock register (see Table 2: M41T66 register map) is used to both set the

clock and to read the date and time from the clock, in a binary coded decimal format.

tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first

four registers.

A WRITE to any clock register will result in the tenths/hundredths of seconds being reset to

“00,” and tenths/hundredths of seconds cannot be written to any value other than “00.”

Bits D0 through D2 of register 04h contain the day (day of week). Registers 05h, 06h, and

07h contain the date (day of month), month, and years. The ninth clock register is the

calibration register (this is described in the clock calibration section). Bit D7 of register 01h

contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When

reset to a '0' the oscillator restarts within one second (typical).

Bit D7 of register 02h (minute register) contains the oscillator fail interrupt enable bit (OFIE).

When the user sets this bit to '1,' any condition which sets the oscillator fail bit (OF) (see

Oscillator stop detection on page 21) will also generate an interrupt output.

Bits D6 and D7 of clock register 06h (century/month register) contain the CENTURY bit 0

(CB0) and CENTURY bit 1 (CB1).

A WRITE to ANY location within the first eight bytes of the clock register (00h-07h),

including the OFIE bit, RS0-RS3 bit, and CB0-CB1 bits will result in an update of the system

clock and a reset of the divider chain. This could result in an inadvertent change of the

current time. These non-clock related bits should be written prior to setting the clock, and

remain unchanged until such time as a new clock time is also written.

The eight clock registers may be read one byte at a time, or in a sequential block. Provision

has been made to assure that a clock update does not occur while any of the eight clock

addresses are being read. If a clock address is being read, an update of the clock registers

will be halted. This will prevent a transition of data during the READ.