M48Z2M1V-85PL1 datasheet(9/20 Pages) STMICROELECTRONICS

9 / 20 page

M48Z2M1Y, M48Z2M1V

Operation modes

Doc ID 5135 Rev 5

9/20

2.2

WRITE mode

The M48Z2M1Y/V is in the WRITE mode whenever W and E are active. The start of a

WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated

by the earlier rising edge of W or E.

The addresses must be held valid throughout the cycle. E or W must return high for

minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE

cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for

tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus

contention; although, if the output bus has been activated by a low on E and G, a low on W

will disable the outputs tWLQZ after W falls.

Figure 6.

WRITE enable controlled, WRITE mode AC waveforms

Note:

Output enable (G) = high.

Figure 7.

Chip enable controlled, WRITE mode AC waveforms

Note:

Output enable (G) = high.

AI02053

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A20

DQ0-DQ7

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

AI02054

tAVAV

tEHAX

tDVEH

A0-A20

DQ0-DQ7

VALID

tAVEH

tAVEL

tAVWL

tELEH

tEHDX

DATA INPUT

M48Z2M1V-85PL1 数据表(PDF) 9 Page - STMicroelectronics

M48Z2M1V-85PL1 数据表(HTML) 9 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

数据表下载