prel

imin

ary

prel

imin

ary

iC-LFS

32x1 LINEAR IMAGE SENSOR

Rev A1, Page 4/9

ELECTRICAL CHARACTERISTICS

Operating Conditions: VCC = VDD = 5 V ±10%, RSET = GND, Tj = -25...85 °C unless otherwise noted

Item

Symbol

Parameter

Conditions

Unit

No.

Min.

Typ.

Max.

Total Device

001

VDD

Digital Supply Voltage Range

4.5

5.5

V

002

VCC

Analogue Supply Voltage Range

4.5

5.5

V

003

I(VDD)

Supply Current in VDD

f(CLK) = 1 MHz

tbd

mA

f(CLK) = 5 MHz

tbd

mA

004

I(VCC)

Supply Current in VCC

tbd

mA

005

Vc()hi

Clamp Voltage hi at SI, CLK, DIS,

RSET

Vc()hi = V() − VCC; I() = 1 mA

0.3

1.8

V

006

Vc()lo

Clamp Voltage lo at SI, CLK, DIS,

RSET

Vc()hi = V() − V(AGND); I() = -1 mA

-1.5

0.3

V

007

Vc()hi

Clamp Voltage hi at AO

Vc()hi = V(AO) − VCC; I(AO) = 1 mA

0.3

1.5

V

008

Vc()lo

Clamp Voltage lo at AO, VCC,

VDD, GND

Vc()lo = V() − V(AGND); I() = -1 mA

-1.5

-0.3

V

Photodiode Array

201

A()

Radiant Sensitive Area

200 µm x 56.40 µm per Pixel

0.01128

mm²

202

S(λ )max

Spectral Sensitivity

λ = 680 nm (see Fig. 1)

0.5

A/W

203

Spectral Application Range

400

980

nm

Analogue Output AO

301

Vs()lo

Saturation Voltage lo

I() = 1 mA

0.5

V

302

Vs()hi

Saturation Voltage hi

Vs()hi = VCC − V(), I() = -1 mA

1

V

303

K

Sensitivity

λ = 680 nm

2.88

V/pWs

304

V0()

Offset Voltage

integration time 1 ms, no illumination

400

800

mV

305

∆

V0()

Offset Voltage Deviation during

integration mode

∆

V0() = V(AO)t1 − V(AO)t2,

∆

t = t2 − t1 = 1 ms

-250

50

mV

306

∆

V()

Signal Deviation during hold

mode

∆

V0() = V(AO)t1 − V(AO)t2,

∆

t = t2 − t1 = 1 ms

-150

150

mV

307

tp(CLK-

AO)

Settling Time

Cl(AO) = 10 pF,

CLK lo → hi until V(AO) = 0.98 x V(VCC)

200

ns

Power-On-Reset

801

VCCon

Power-On Release by VCC

4.4

V

802

VCCoff

Power-Down Reset by VCC

1

V

803

VCChys

Hysteresis

VCChys = VCCon − VCCoff

0.4

1

2

V

Bias Current Adjust RSET

901

Ibias()

Permissible External Bias Current

20

100

µA

902

Vref

Reference Voltage

I(RSET) = Ibias

2.5

3

3.5

V

Input Interface SI, CLK, DIS

B01

Vt()hi

Threshold Voltage hi

1.4

1.8

V

B02

Vt()lo

Threshold Voltage lo

0.9

1.2

V

B03

Vt()hys

Hysteresis

Vt()hys = Vt()hi − Vt()lo

300

800

mV

B04

I()

Pull-Down Current

10

30

50

µA

B05

fclk

Permissible Clock Frequency

5

MHz