ISDN TA POTS Interface

CMX625

 2001 Consumer Microcircuits Limited

21

D/625/2

The CMX625 is programmed via the ‘MON1’ (Monitor Channel 1) channel in TE mode and the ‘Monitor’

channel in non-TE mode. The programming sequence consists of 3 consecutive Monitor bytes: the IOM-2

address, the CMX625 command and data byte. Before executing a command, the CMX625 compares the

received IOM-2 address byte with its own address. The MSB of the IOM-2 address is always a ‘1’ (see

section 1.5.2). A logical ‘1’ in the MSB of the CMX625 command represents a write operation and a

logical ‘0’ represents a read operation.

Structure for Register read/write operations:

IOM

Command

Register

R/W

0=Read

1=Write

0

X

X

Register

Address

A3

Register

Address

A2

Register

Address

A1

Register

Address

A0

Example 1: Program the CMX625 to generate interrupt requests for DTMF RX Status Change on bit 5 of

C/I channel, i.e. C/I1 Channel Output Control Code (2-0)=110. Set IOM-2 address to SA2-SA0=010 and

device select, DS=1.

MX

(DD)

MR

(DU)

DD

(hex)

MX

(DU)

MR

(DD)

DU

(hex)

Comment

1

1

FF

1

1

FF

Monitor Channel Idle State

0

1

A8

1

1

FF

Transmit IOM-2 Address

0

0

A8

1

1

FF

Acknowledge Address

1

0

88

1

1

FF

Transmit Command (Write IOM-2 Control, $8)

0

1

88

1

1

FF

1

0

06

1

1

FF

Acknowledge Command/ Transmit IOM-2 Control Data

0

1

06

1

1

FF

1

0

FF

1

1

FF

Acknowledge Data

1

1

FF

1

1

FF

End of Transmission

0

1

A8

1

1

FF

Transmit IOM-2 Address

0

0

A8

1

1

FF

Acknowledge Address

1

0

89

1

1

FF

Transmit Command (Write Mask Register, $9)

0

1

89

1

1

FF

1

0

20

1

1

FF

Acknowledge Command/ Transmit IOM-2 Control Data

0

1

20

1

1

FF

1

0

FF

1

1

FF

Acknowledge Data

1

1

FF

1

1

FF

End of Transmission

1

1

FF

1

1

FF

Idle

If the command is a register read then only the address and command bytes are sent. The CMX625 will

respond with an IOM-2 Register address byte followed by the read data. The IOM-2 Register address byte

consists of the Register address that is being read in the least significant 4 bits and the IOM-2 address

(less the device select bit) in the most significant 4 bits.