4

V

BIAS

XTAL/CLOCK

V

DD

V

DD

SERIAL CLOCK

COMMAND DATA

V

SS

REPLY DATA

AUDIO OUT

AUDIO IN

V

SS

A9

A8

A7

A6

A5

A4

A3/ECK

A2/DCK

A1/DEI

A0/ENO

4 x 1Mbit

DRAM

C

1

5

4

R

2

X

1

XTAL/CLOCK

V

SS

INSET

See INSET

C

4

C

5

V

SS

§

FX802J

R

1

C S

R A S 4

XTAL

FX802J

13

14

1

2

3

4

5

6

7

8

9

10

11

12

15

16

17

18

19

20

21

22

23

24

25

26

27

28

§

§

§

§

C

6

R

3

D

RAS

CAS

WE

A0 – A9

Q

RAS

CAS

WE

A0 – A9

D

Q

WE

A0 – A9

D

Q

CAS

RAS

XTAL

R A S 2

R A S 1

W E

IRQ

C A S

R A S 3

A0 – A9

D

Q

CAS

WE

RAS

External Components

Component

Value

R

1

=

22.0k

Ω

R

2

1.0M

Ω

R

3

1.0k

Ω

C

1

1.0

µF

C

2

33.0pF

C

3

33.0pF

C

4

=

1.0

µF

C

5

1.0

µF

C

6

1.0nF

X

1

4.00MHz

or

4.032MHz

or

4.096MHz

Tolerance: R =

±10% C = ±20%

Fig.2 Recommended Component and DRAM Connections

Notes

1. Xtal circuitry shown INSET is in accordance with CML

Application Note D/XT/2 December 1991.

2. External Xtal circuitry is not applicable to the 24-pin/lead

versions of this device, only a clock pulse input can be

used.

3. Functions whose pins are marked § above are not

available on the 24-pin/lead versions of this device. Pin

numbers illustrated are for 28-pin versions.

4. Table 3 details the actual encoder/decoder sample rates

available using the Xtal frequencies recommended above.

5. R

“C-BUS” Interrupt Request (IRQ) line, the optimum value

will depend upon the circuitry connected to the IRQ line.

Up to 8 peripherals may be connected to this line.

6. Recommended DRAM Parameters:

256kbit x 1 or 1Mbit x 1 Dynamic Random Access Memory

with ‘CAS before RAS’ refresh mode, maximum Row

Address Access time = 200nsec.

Example DRAM types:

256kbit (262,144bits)

Texas Instruments

TMS4256–20

Hitachi

HM51256–15

1Mbit (1,048,576bits)

Texas Instruments

TMX4C1024–15

Hitachi

HM511000–15

7. Figure 2 (above) shows connections to 4 x 1Mbit sections

of DRAM. If desired, to simplify PCB layout, the DRAM

inputs A0 to A8 may be connected in any order to the

FX802 DVSR Codec output pins A0 to A8. Connections to

256kbit DRAM are similar, but A9 unconnected.

8. When using the FX802 “stand-alone (Direct Access),” no

DRAM should be connected.