4-Level FSK Modem Data Pump

FX929A

© 1996 Consumer Microcircuits Limited

21

D/929A/4

t3

t3

t3

Modem Rx input

Symbols to

De-interleave circuit

Data from Data Block Buffer

Task to Command Register

for task #1

for task #2

for task #3

1

2

3

1

2

3

t6

t6

t6

t7

t7

t7

BFREE bit

Figure 11 Receive Task Timing Diagram

Task

Time

(symbol times)

t3

Time to receive all symbols of task

SFS

25 (minimum)

SFP

48 (minimum)

RSID

23

RHB/RILB

69

R4S

4

t6

Maximum time between first symbol of task

SFS

21

entering the de-interleave circuit and the

SFP

21

task being written to modem.

RSID

15

RHB/RILB

51

R4S

3

t7

Maximum time from the last bit of the task

Any

1

entering the de-interleave circuit to BFREE

going to a logic '1' (high)

RRC Filter Delay

The previous task timing figures are based on the signal at the input to the RRC filter (in transmit mode) or the

input to the de-interleave buffer (in receive mode). There is an additional delay of about 8 symbol times through

to the RRC filter in both transmit and receive modes, as illustrated below:

Symbol-times

Tx Symbol to RRC Filter

Rx Symbo l to D e-int erleave Buffer

Tx Symbol at Txop pin / Rx Symbo l from FM discriminator

Figure 12 RRC Low Pass Filter Delay