| 数据搜索系统,热门电子元器件搜索 |
|
AP7167 数据表(PDF) 4 Page - Diodes Incorporated |
|
|
|||||||||||||||||||||||||||||
AP7167 数据表(HTML) 4 Page - Diodes Incorporated |
|
4 / 14 page ![]() AP7167 1.2A LOW DROPOUT REGULATOR WITH POK AP7167 Document number: DS31252 Rev. 7 - 2 4 of 14 www.diodes.com September 2010 © Diodes Incorporated Electrical Characteristics (TA = 25 oC, V IN = VOUT +1V, CIN = 1µF, COUT = 10µF, VEN = VIN, unless otherwise stated) Symbol Parameter Test Conditions Min Typ. Max Unit IQ Input Quiescent Current IOUT= 0 ⎯ 125 180 µA ISHDN Input Shutdown Current VEN = 0V, IOUT = 0 (Note 3) -1 0.1 1 µA VDropout Dropout Voltage VOUT ≥ 1.5V, IOUT = 0.5A 230 mV VOUT ≥ 1.5V, IOUT = 1A 500 800 mV VREF FB reference voltage 0.8 V IFB FB leakage ⎯ 0.01 1 µA VOUT Output Voltage Total Accuracy Over line, load and temperature -3 3 % OUT IN OUT V ΔV ΔV / Line Regulation VIN = VOUT +1V to 5.5V, IOUT = 1mA 0.02 %/V ΔV OUT / VOUT Load Regulation IOUT from 1mA to 1A -1.5 1.5 % tST Start-up Time, from EN high to POK high VEN = 0V to 2.0V, IOUT = 100mA, VIN = 3.3V 190 µs PSRR Power Supply Rejection Ratio 1kHz, VIN = 3.3V, VOUT = 1.2V, IOUT = 100mA 60 dB ILIMIT Current limit VOUT = 1.8V, ROUT = 0.5Ω 1.2 1.6 A ISHORT Short-circuit Current VIN = 3.3V, VOUT < 0.2V 750 mA VIL EN Input Logic Low Voltage 0.4 V VIH EN Input Logic High Voltage 1.4 V IEN EN Input leakage VEN = 0V or 5.5V ⎯ 0.01 1 µA VOL POK output low voltage Force 2mA 100 200 mV VPOK_TH_UP Output voltage (rising) POK threshold FB (or OUT for fixed version) rising 87% 92% 97% Vref VPOK_Hys Output voltage POK hysteresis 4% Vref POK deglitch VIN = 3.3V, VOUT = 1.2V 160 µs IPOK_LK POK leakage current VPOK = 5.5V ⎯ 0.01 1 µA TSHDN Thermal shutdown threshold 155 °C THYS Thermal shutdown hysteresis 25 °C θJA Thermal Resistance Junction-to- Ambient DFN3030-10 (Note 4) 40 oC/W SOP-8L-EP (Note 5) 27 oC/W Notes: 3. POK pin must be disconnected from IN pin. 4. Test condition for DFN3030-10: Device mounted on FR-4 2-layer board, 2oz copper, with minimum recommended pad on top layer and 6 vias to bottom layer 1.0”x1.5” ground plane. 5. Test condition for SOP-8L-EP: Device mounted on 2" x 2" FR-4 substrate PCB, 2oz copper, with minimum recommended pad on top layer and thermal vias to bottom layer ground plane. Typical Performance Characteristics |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |