MPC8360E datasheet(21/108 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor

DDR and DDR2 SDRAM

Table 15 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.

Table 16 provides the recommended operating conditions for the DDR SDRAM component(s) of the

device when GVDD(typ) = 2.5 V.

Input current (0 V

≤VIN ≤ OVDD)IIN

—±10

μA—

Notes:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to equal 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise

on MVREF cannot exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal

MVREF. This rail should track variations in the DC level of MVREF.

4. Output leakage is measured with all outputs disabled, 0 V

≤ V

OUT ≤ GVDD.

Table 15. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS, DQS

CIO

Delta input/output capacitance: DQ, DQS, DQS

CDIO

—0.5

Note:

1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.

Table 16. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O supply voltage

GVDD

2.375

2.625

I/O reference voltage

MVREF

0.49

× GVDD

0.51

× GVDD

I/O termination voltage

VTT

MVREF – 0.04

MVREF + 0.04

Input high voltage

VIH

MVREF + 0.18

GVDD + 0.3

—

Input low voltage

VIL

–0.3

MVREF – 0.18

—

Output leakage current

IOZ

—±10

μA4

Output high current (VOUT = 1.95 V)

IOH

–15.2

—

Output low current (VOUT = 0.35 V)

IOL

15.2

—

MVREF input leakage current

IVREF

—±10

μA—

Input current (0 V

≤VIN ≤ OVDD)IIN

—±10

μA—

Notes:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of MVREF.

4. Output leakage is measured with all outputs disabled, 0 V

≤ VOUT ≤ GVDD.

Table 14. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V (continued)

Parameter/Condition

Symbol

Min

Max

Unit

Notes

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