R5F3640ECNFB datasheet(84/91 Pages) RENESAS

84 / 91 page

R01DS0016EJ0100 Rev.1.00

Page 84 of 88

Feb 07, 2011

M16C/64C Group

5. Electrical Characteristics

VCC1 = VCC2 = 3 V

Switching Characteristics

(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.3.4.2

In 1 to 3 Waits Setting and When Accessing External Area

Notes:

Calculated according to the BCLK frequency as follows:

This standard value shows the timing when the output is

off, and does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-

up (pull-down) resistance value.

Hold time of data bus is expressed in

−CR × ln(1−V

OL/VCC2)

by a circuit of the right figure.

For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ,

hold time of output low level is

t =

−30 pF × 1 kΩ × In(1 − 0.2V

CC2/VCC2)

= 6.7 ns.

Calculated according to the BCLK frequency as follows:

Hold time is equal to or less than 0 ns when the BCLK frequency exceeds 20 MHz.

Table 5.56

Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When

Accessing External Area)

Symbol

Parameter

Measuring

Condition

Standard

Unit

Min.

Max.

td(BCLK-AD)

Address output delay time

See

Figure 5.27

th(BCLK-AD)

Address output hold time (in relation to BCLK)

0ns

th(RD-AD)

Address output hold time (in relation to RD)

0ns

th(WR-AD)

Address output hold time (in relation to WR)

(Note 2)

td(BCLK-CS)

Chip select output delay time

th(BCLK-CS)

Chip select output hold time (in relation to BCLK)

0ns

td(BCLK-ALE)

ALE signal output delay time

th(BCLK-ALE)

ALE signal output hold time

-4

td(BCLK-RD)

RD signal output delay time

th(BCLK-RD)

RD signal output hold time

0ns

td(BCLK-WR)

WR signal output delay time

th(BCLK-WR)

WR signal output hold time

0ns

td(BCLK-DB)

Data output delay time (in relation to BCLK)

td(DB-WR)

Data output delay time (in relation to WR)

(Note 1)

th(WR-DB)

Data output hold time (in relation to WR) (3)

(Note 4)

n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.

When n = 1, f(BCLK) is 12.5 MHz or less.

0.5

–

() 10

BCLK

()

------------------------------------40 ns

[]

–

0.5

BCLK

()

----------------------15 ns

[]

–

DBi

0.5

BCLK

()

----------------------25 ns

[]

–

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