LTM4607 datasheet(18/32 Pages) LINER

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LTM8042/LTM8042-1

80421fa

APPLICATIONS INFORMATION

PCB Layout

Most of the headaches associated with PCB layout have

been alleviated or even eliminated by the high level of

integration of the LTM8042/LTM8042-1. The device is

nevertheless a switching power supply, and care must be

taken to minimize EMI and ensure proper operation. Even

with the high level of integration, you may fail to achieve

specified operation with a haphazard or poor layout. See

Figures 2, 3 and 4 for suggested layouts of boost, buck

and buck-boost operating modes.

Ensure that the grounding and heat sinking are acceptable.

A few rules to keep in mind are:

1. Place the RT resistor as close as possible to its re-

spective pins.

2. Place the CIN and CVCC capacitor as close as possible

to the VIN and GND connections of the LTM8042/

LTM8042-1.

3. Place the COUT capacitor as close as possible to the

BSTOUT/BKIN or BSTIN/BKLED– and GND connection

of the LTM8042/LTM8042-1.

BSTOUT/BKIN

BSTIN/BKLED–

LED+

GND

VIN

TGEN

80421 F02

TO LED STRING

CTL

VCC

CVCC

CIN

COUT

THERMAL VIAS TO GROUND PLANE

GND

Figure 2. Suggested Layout for Boost Operation

4. Place the CIN, CVCC and COUT capacitors such that their

ground current flows directly adjacent to or underneath

the LTM8042/LTM8042-1.

5. Connect all of the GND connections to as large a copper

pour or plane area as possible on the top layer. Avoid

breaking the ground connection between the external

components and the LTM8042/LTM8042-1.

Use vias to connect the GND copper area to the board’s

internal ground planes. Liberally distribute these GND vias

to provide both a good ground connection and thermal

path to the internal planes of the printed circuit board.

Pay attention to the location and density of the thermal

vias in Figures 2 through 4. The LTM8042/LTM8042-1

can benefit from the heat sinking afforded by vias that

connect to internal GND planes at these locations, due to

their proximity to internal power handling components.

The optimum number of thermal vias depends upon the

printed circuit board design. For example, a board might

use very small via holes. It should employ more thermal

vias than a board that uses larger holes.

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