TRIGGER Input (TRIG, Pin 14)

A transition at the TRIG input causes OUT to switch with or without de-

lay, depending on the selected mode. The TRIG input to OUT transition

relation is always opposite in polarity, with the exception of One-Shot

mode. (See Mode definitions above.) TRIG input has an internal pull-

down resistor of about 500kΩ and is buffered by a Schmitt trigger to pro-

vide input hysteresis.

LS7215 TIME BASE Input (RC/CLOCK, Pin 4)

For

LS7215, the basic timing signal is applied at the RC/CLOCK input.

The clock can be provided from either an external source or generated

by an internal oscillator by connecting an R-C network to this input. The

frequency of oscillation is given by

ƒ 1/RC. Chip-to-chip oscillation

tolerance is ± 5% for a fixed value of RC.

The external clock mode is selected by applying a logic low to the RCS/

CLKS input (Pin 5); the internal oscillator mode is selected by applying a

high level to the RCS/CLKS input.

LS7216 TIME BASE Input (XTLI/CLOCK, Pin 4)

For

LS7216, the basic timing clock is applied to the XLTI/CLOCK input

from either an external clock source or generated by an internal crystal

oscillator by connecting a crystal between XTLI/CLOCK input and the

XTLO output (Pin 5).

LS7215 TIME BASE SELECT Input (RCS/CLKS, Pin 5)

For

LS7215, the external clock operation at Pin 4 is selected by ap-

plying a logic low to the RCS/CLKS input. The internal oscillator option

with RC timer at Pin 4 is selected by applying a logic high at the RCS/

CLKS input. RCS/CLKS input has an internal pull-down resistor of about

500kΩ.

LS7216 TIME BASE Output (XTLO, Pin 5)

For

LS7216, when a crystal is used for generating the time base oscilla-

tion, the crystal is connected between XTLI/CLOCK and XTLO pins.

PRESCALER SELECT Input (PSCLS, Pin 6)

The PSCLS input is a 3-state input, which selects one of three prescale

factors according to Table 2.

TABLE 2. PRESCALE FACTOR SELECTION

PSCLS Input

S (Prescale Factor)

Logic Level

LS7215

LS7216

Float

1

1

3000

32768

3600

32768 x 60

Using prescale factors of 3000 and 3600, delays in units of minutes can

be produced from 50Hz and 60Hz line sources. Prescale factors of

32,768 and 32,768 x 60 can be used to generate accurate delays in

units of seconds and minutes, respectively, from a 32kHz watch crystal.

TIMER RESET Input (RESET, Pin 7)

When RESET input switches high, any timeout in progress is aborted

and OUT switches high without delay. With RESET high, OUT remains

high. When RESET switches low with TRIG low in any mode, OUT re-

mains high. When RESET switches low with TRIG high in Delayed Op-

erate and Dual Delay modes, the delay timer is started and OUT switch-

es low at the end of the delay timeout. When RESET switches low with

TRIG high in Delayed Release mode, OUT switches low without delay.

When RESET switches low with TRIG high in One-Shot mode, OUT re-

mains high. RESET input has an internal pull-down resistor of about

500kΩ and is buffered by a Schmitt Trigger to provide input hysteresis.

7215-072009-2

Supply voltage negative terminal or GND.

DELAY Output (OUT, Pin 9)

Except in One-Shot mode, OUT switches with or without delay (de-

pending on mode) in inverse relation to the logic level of the TRIG in-

put. In One-Shot mode, a timed low level is produced at OUT, in re-

sponse to a positive transition of the TRIG input.

LOAD Input (LOAD, Pin 20)

The LOAD input allows the weighting bits, WB0 - WB7, to be latched

from a shared bus, such as a MCU IO port. When the LOAD is low,

the internal weighting bits dynamically follow the data presented at the

WB0 - WB7 inputs. When the LOAD is switched high, the WB0 - WB7

data become latched, freeing up the bus to service other peripheral

OPEN DRAIN DELAY Output (ODOUT, Pin 10)

The ODOUT is the open drain version of the delay output which en-

ables the chip to directly drive a relay, operating at a voltage higher

than the chip supply voltage through a single NPN transistor (see Fig-

ure 10) . Functionally, the ODOUT is identical to the other delay out-

put, OUT.

WEIGHTING BIT Inputs (WB7 to WB0, Pins 11 - 18)

Inputs WB0 through WB7 are binary weighted delay bits used to pro-

gram the delay according to the following relations:

One-Shot Mode: Pulse width = SW

ƒ

All other Modes: Delay = SW + 0.5

ƒ

Where:

S = Prescale factor (See Table 2)

ƒ = Time base frequency at Pin 4

W = WB0 + WB1 + ....... WB7

The weighting factor, W, is calculated by substituting in the equation

above for W, the weighted values for all the WB inputs that are at logic

high. The weighted values for the WB inputs are shown in Table 3.

Each WB input has an internal pull-down resistor of about 500kΩ.

TABLE 3. BIT WEIGHTS

BITS

VALUE

WB0

1

WB1

2

WB2

4

WB3

8

WB4

16

WB5

32

WB6

64

WB7

128

Supply voltage positive terminal.

The information included herein is believed to be ac-

curate and reliable. LSI Computer Systems, Inc. as-

sumes no responsibilities for inaccuracies, nor for any

infringements of patent rights of others which may re-

sult from its use.