CY2DP1510

Document Number: 001-55566 Rev. *G

Page 3 of 13

Pinouts

Figure 1. Pin Diagram – 32-Pin TQFP Package

12

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

Q2#

Q2

Q1#

Q1

Q0#

Q0

Q7

Q7#

Q8

Q8#

Q9

Q9#

CY2DP1510

Table 1. Pin Definitions

Pin No.

Pin Name

Pin Type

Description

1, 9, 16, 25, 32

Power

Power supply

2

IN_SEL

Input

Input clock select pin. Low-voltage complementary metal oxide

semiconductor (LVCMOS)/low-voltage transistor-transistor-logic (LVTTL).

When IN_SEL = Low, the IN0/IN0# differential input pair is active

When IN_SEL = High, the IN1/IN1# differential input pair is active

3

IN0

Input

LVPECL input clock. Active when IN_SEL = Low

4

IN0#

Input

LVPECL complementary input clock. Active when IN_SEL = Low

Output

LVPECL reference voltage output

6

IN1

Input

LVPECL input clock. Active when IN_SEL = High

7

IN1#

Input

LVPECL complementary input clock. Active when IN_SEL = High

Power

Ground

10,12,14,17,19,21,

23,26,28,30

Q(0:9)#

Output

LVPECL complementary output clocks

11,13,15,18,20,22,

24,27,29,31

Q(0:9)

Output

LVPECL output clocks

–

EPAD

–

Exposed paddle. Connect to ground plane for package heat dissipation.

No electrical connection.

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