MPC5634M datasheet(113/132 Pages) FREESCALE

113 / 132 page

MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

113

4.16.6

eQADC SSI timing

Figure 29. eQADC SSI timing

Table 38. eQADC SSI timing characteristics (pads at 3.3 V or at 5.0 V)1

1 SS timing specified at f

SYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.25 V, TA = TL to TH, and CL =50pF

with SRC = 0b00.

CLOAD = 25pF on all outputs. Pad drive strength set to maximum.

Symbol

Rating

Min

Typ

Max

Unit

1fFCK

FCK Frequency 2, 3

2 Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays.

3 FCK duty is not 50% when it is generated through the division of the system clock by an odd number.

1/17 fSYS_CLK

2 f

SYS_CLK

Hertz

1tFCK

FCK Period (tFCK = 1/ fFCK)

2 tSYS_CLK

17tSYS_CLK

seconds

2tFCKHT CC

Clock (FCK) High Time

tSYS_CLK  6.5

9* tSYS_CLK  6.5

3tFCKLT

Clock (FCK) Low Time

tSYS_CLK  6.5

8* tSYS_CLK  6.5

4tSDS_LL CC

SDS Lead/Lag Time

–7.5

+7.5

5tSDO_LL CC

SDO Lead/Lag Time

–7.5

+7.5

6tDVFE

Data Valid from FCK Falling Edge

(tFCKLT+tSDO_LL)

1ns

7tEQ_SU CC

eQADC Data Setup Time (Inputs)

8tEQ_HO CC

eQADC Data Hold Time (Inputs)

1st (MSB)

2nd

25th

26th

1st (MSB)

2nd

25th

26th

FCK

SDS

SDO

External Device Data Sample at

SDI

eQADC Data Sample at

FCK Falling Edge

FCK Rising Edge

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