MPC5634M datasheet(13/132 Pages) FREESCALE

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MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

— Memory management unit (MMU) with 16-entry fully-associative translation look-aside buffer (TLB)

— Separate instruction bus and load/store bus

— Vectored interrupt support

— Interrupt latency < 120 ns @ 80 MHz (measured from interrupt request to execution of first instruction of interrupt

exception handler)

— Non-maskable interrupt (NMI) input for handling external events that must produce an immediate response, e.g.,

power down detection. On this device, the NMI input is connected to the Critical Interrupt Input. (May not be

recoverable)

— Critical Interrupt input. For external interrupt sources that are higher priority than provided by the Interrupt

Controller. (Always recoverable)

— New ‘Wait for Interrupt’ instruction, to be used with new low power modes

— Reservation instructions for implementing read-modify-write accesses

— Signal processing extension (SPE) APU

– Operating on all 32 GPRs that are all extended to 64 bits wide

– Provides a full compliment of vector and scalar integer and floating point arithmetic operations (including

integer vector MAC and MUL operations) (SIMD)

– Provides rich array of extended 64-bit loads and stores to/from extended GPRs

– Fully code compatible with e200z6 core

— Floating point

– IEEE 754 compatible with software wrapper

– Scalar single precision in hardware, double precision with software library

– Conversion instructions between single precision floating point and fixed point

– Fully code compatible with e200z6 core

— Long cycle time instructions, except for guarded loads, do not increase interrupt latency

— Extensive system development support through Nexus debug port

•

Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR)

— Three master ports, four slave ports

– Masters: CPU Instruction bus; CPU Load/store bus (Nexus); eDMA

– Slave: Flash; SRAM; Peripheral Bridge; calibration EBI

— 32-bit internal address bus, 64-bit internal data bus

•

Enhanced direct memory access (eDMA) controller

— 32 channels support independent 8-bit, 16-bit, or 32-bit single value or block transfers

— Supports variable sized queues and circular queues

— Source and destination address registers are independently configured to post-increment or remain constant

— Each transfer is initiated by a peripheral, CPU, or eDMA channel request

— Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block

transfer

•

Interrupt controller (INTC)

— 191 peripheral interrupt request sources

— 8 software settable interrupt request sources

— 9-bit vector

– Unique vector for each interrupt request source

– Provided by hardware connection to processor or read from register

— Each interrupt source can be programmed to one of 16 priorities

— Preemption

– Preemptive prioritized interrupt requests to processor

MPC5634M 数据表(PDF) 13 Page - Freescale Semiconductor, Inc

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