Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com

Package and Pinout

Table 3. Pinout

Pin #

Symbol

Function

1

NC

No Internal Connection is made

2

NC

No Internal Connection is made

3

GND

Electrical and Lid Ground

4f

O

Output Frequency

5Cf

O

Complementary Output Frequency

6V

DD

Supply Voltage

Figure 3. Package Outline Drawing

7.0±0.15

5.0±0.15

1.40

1.20

3.57

2.54

5.08

VC-708

Frequency

Date Code

1

3

1

Bottom View

5

2

23

65

4

64

1.8 max

Figure 2. Pad Layout

1.96

3.66

5.08

2.54

1.78

LVPECL Application Diagrams

The VC-708 incorporates a standard PECL output scheme, which are unterminated FET drains. There are numerous application notes on terminating and

interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 4, and a pull-up/pull-down scheme as shown in Figure 5.

AC coupling capacitor are optional, depending on the application and the input logic requirements of the next stage.

1

2

3

6

5

4

NC

NC

140

140

0.01uF

0.01uF

0.01uF

Figure 4. Single Resistor Termination Scheme

Resistor values are typically 140 ohms for 3.3V operation and

84 ohms for 2.5V operation.

Figure 5. Pull-Up Pull Down Termination

Resistor values shown are typical for 3.3 V opertaion.

For 2.5V operation, the resistor to ground is 62 ohms and

the resistor to supply is 250 ohms

One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left untermi-

nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching

into account. Load matching and power supply noise are the main contributors to jitter related problems.

Units are mm

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