5

SPDT AlGaAs PIN Diode Switch

Rev. V5

MA4AGSW2

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• India Tel: +91.80.43537383

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Visit www.macomtech.com for additional data sheets and product information.

M/A-COM Technology Solutions Inc. and its affiliates reserve the right to make

changes to the product(s) or information contained herein without notice.

ADVANCED: Data Sheets contain information regarding a product M/A-COM Technology Solutions

is considering for development. Performance is based on target specifications, simulated results,

and/or prototype measurements. Commitment to develop is not guaranteed.

PRELIMINARY: Data Sheets contain information regarding a product M/A-COM Technology

Solutions has under development. Performance is based on engineering tests. Specifications are

typical. Mechanical outline has been fixed. Engineering samples and/or test data may be available.

Commitment to produce in volume is not guaranteed.

Operation of the MA4AGSW2 Switch

The simultaneous application of a negative DC current to the low loss port and positive DC current to the

remaining isolated switching port is required for the operation of the MA4AGSW2, AlGaAs, PIN switch. The

backside area of the die is the RF and DC return ground plane. The DC return is connected to the common port

J1. The forward bias voltage at J2 & J3 will not exceed ±1.6 volts and is typically ± 1.4 volts with supply current of

± 30mA). In the low loss state, the series diode must be forward biased and the shunt diode reverse biased. While

for the Isolated port, the shunt diode is forward biased and the series diode is reverse biased. The bias network

design shown below should yield > 30 dB RF to DC Isolation.

Available for use in conjunction with M/A-COM Tech’s line of AlGaAs switches are two, fully integrated, broad-

band, monolithic, bias networks which may be used as an alternative to the suggested individual component bias

network shown below. Refer to datasheets for the MA4BN1840-1 and MA4BN1840-2 for additional information.

The lowest insertion loss, P1dB, IP

return path, (J1). A minimum value of | -2V | is recommended at this return node, which is achievable with a

standard, ± 5V TTL Controlled PIN Diode Driver.

MA4AGSW2 Schematic with a Typical External 2-18 GHz Bias Network

TYPICAL DRIVER CONNECTIONS

CONTROL LEVEL (DC CURRENT)

RF OUTPUT STATE

J2

J3

J2-J1

J3-J1

-10mA

+10mA

Low Loss

Isolation

+10mA

-10mA

Isolation

Low Loss