MPC8306EC datasheet(2/76 Pages) FREESCALE

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MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

Overview

The MPC8306 incorporates the e300c3 (MPC603e-based) core built on Power Architecture® technology,

which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and on-chip memory

management units (MMUs). The MPC8306 also includes two DMA engines and a 16-bit DDR2 memory

controller.

A new communications complex based on QUICC Engine technology forms the heart of the networking

capability of the MPC8306. The QUICC Engine block contains several peripheral controllers and a 32-bit

RISC controller. Protocol support is provided by the main workhorses of the device — the unified

communication controllers (UCCs). A block diagram of the MPC8306 is shown in Figure 1.

Figure 1. MPC8306 Block Diagram

Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps

EthernetIEEE-1588, and HDLC.

1 RMII/MII

2x TDM Ports

16-KB

D-Cache

16-KB

I-Cache

e300c3 Core with Power

2x DUART

Interrupt

I2C

Timers

GPIO

DDR2

Controller

Baud Rate

Generators

Accelerators

Single 32-bit RISC CP Serial DMA

Serial Interface

QUICC Engine™ Block

Time Slot Assigner

16 KB Multi-User RAM

FPU

Management

SPI

RTC

Bus Controller

2x HDLC

2 RMII/MII

2x IEEE 1588

USB 2.0 HS

Host/Device/OTG

ULPI

DMA

4 FlexCAN

eSDHC

48 KB Instruction RAM

Engine

Enhanced Local

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