MPC8309EC datasheet(13/82 Pages) FREESCALE

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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the MPC8309.

NOTE

The rise/fall time on QUICC Engine input pins should not exceed 5 ns. This

should be enforced especially on clock signals. Rise time refers to signal

transitions from 10% to 90% of OVDD; fall time refers to transitions from

90% to 10% of OVDD.

4.1

DC Electrical Characteristics

Table 7 provides the clock input (SYS_CLK_IN/PCI_SYNC_IN) DC specifications for the MPC8309.

These specifications are also applicable for QE_CLK_IN.

4.2

AC Electrical Characteristics

The primary clock source for the MPC8309 can be one of two inputs, SYS_CLK_IN or PCI_SYNC_IN,

depending on whether the device is configured in PCI host or agent mode. Table 8 provides the clock input

(SYS_CLK_IN/PCI_SYNC_IN) AC timing specifications for the MPC8309. These specifications are also

applicable for QE_CLK_IN.

Table 7. SYS_CLK_IN DC Electrical Characteristics

Parameter

Condition

Symbol

Min

Max

Unit

Input high voltage

—

VIH

2.4

OVDD +0.3

Input low voltage

—

VIL

–0.3

0.4

SYS_CLK_IN input current

0 V

 V

IN  OVDD

IIN

—±5

A

SYS_CLK_IN input current

0 V

 V

IN  0.5 V or

OVDD – 0.5 V  VIN OVDD

IIN

—±5

A

SYS_CLK_IN input current

0.5 V

 V

IN  OVDD – 0.5 V

IIN

—±50

A

Table 8. SYS_CLK_IN AC Timing Specifications

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

SYS_CLK_IN frequency

fSYS_CLK_IN

—

66.67

MHz

SYS_CLK_IN cycle time

tSYS_CLK_IN

—

41.6

—

SYS_CLK_IN rise and fall time

tKH, tKL

1.1

—

2.8

PCI_SYNC_IN rise and fall time

tPCH, tPCL

1.1

—

2.8

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