Serial Interface and Device Control

A CMOS-compatible serial interface controls the

MAX9972 modes (Figure 4). Control data flow into a 12-

bit shift register (LSB first) and are latched when CS is

taken high. Data from the shift register are then loaded

to the per-channel control latches as determined by

bits D8–D11, and indicated in Figure 4 and Table 4.

The latches contain the six mode bits for each channel

of the device. The mode bits, in conjunction with exter-

nal inputs DATA_ and RCV_, manage the features of

each channel. Transfer data asynchronously from the

input registers to the channel registers by forcing LD

low. With LD always low, data transfer on the rising

edge of CS.

Quad, Ultra-Low-Power, 300Mbps ATE

Drivers/Comparators

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19

Table 4. Control Register Bit Functions

BIT STATE

BIT

NAME

FUNCTION

01

POWER-UP

STATE

0

TERM

Term Mode Control

High Impedance

Term Mode

0

1

LLEAK

Assert Low-Leakage Mode

Term Mode

Low Leakage

0

2

SENSE EN

Enable Sense Switch

Disabled

Enabled

0

3

FORCE EN

Enable Force Switch

Disabled

Enabled

0

4

LOAD EN LOW

Enable Low Load Resistor

Disabled

Enabled

0

5

LOAD EN HIGH

Enable High Load Resistor

Disabled

Enabled

0

6

—

Unused

X

X

0

7

—

Unused

X

X

0

8

CH1

Update Channel 1 Control Register

Disabled

Enabled

1

9

CH2

Update Channel 2 Control Register

Disabled

Enabled

1

10

CH3

Update Channel 3 Control Register

Disabled

Enabled

1

11

CH4

Update Channel 4 Control Register

Disabled

Enabled

1

MAX9972

SCLK

DIN

CS

LD

ENABLE

QUAD F/F

D

Q

ENABLE

0–5

8

MODE BITS

CHANNEL 4

MODE BITS

CHANNEL 3

MODE BITS

CHANNEL 2

MODE BITS

CHANNEL 1

LOAD

QUAD F/F

D

Q

ENABLE

0–5

9

LOAD

QUAD F/F

D

Q

ENABLE

0–5

10

LOAD

QUAD F/F

D

Q

ENABLE

0–5

11

6

6

6

6

LOAD

11

10

9

8

7

6

5

4

3

2

1

0

Figure 4. Serial Interface