Click To Buy

Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or

other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.

FEATURES 

HIGH  GAIN  

LOW OUTPUT CAPACITANCE 

100MHz 

ABSOLUTE MAXIMUM RATINGS 

@ 25°C (unless otherwise noted) 

Maximum Temperatures 

Storage Temperature ‐65°C to +200°C 

Operating Junction Temperature ‐55°C to +150°C 

Maximum Power Dissipation 

Continuous Power Dissipation (One side) 

250mW 

Continuous Power Dissipation (Both sides) 

500mW 

Linear Derating factor (One side) 

2.3mW/°C 

Linear Derating factor (Both sides) 

4.3mW/°C 

Maximum Currents 

Collector Current 

5mA 

  

MATCHING CHARACTERISTICS @ 25°C (unless otherwise stated) 

SYMBOL 

CHARACTERISTIC 

MIN 

TYP 

MAX 

UNITS 

CONDITIONS 

Base Emitter Voltage Differential 

‐‐ 

0.2 

1 

mV 

 

Base Emitter Voltage Differential 

Change with Temperature 

‐‐ 

1 

5 

µV/°C 

TA = ‐55°C to +125°C 

Base Current Differential 

‐‐ 

1 

5 

nA 

DC Current Gain Differential 

‐‐ 

5 

‐‐ 

% 

 

ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)

SYMBOL 

CHARACTERISTICS 

MIN. 

TYP. 

MAX. 

UNITS 

CONDITIONS 

Collector to Base Voltage 

35 

‐‐ 

‐‐ 

V 

Collector to Emitter Voltage 

35 

‐‐ 

‐‐ 

V 

Emitter‐Base Breakdown Voltage 

6.2 

‐‐ 

‐‐ 

V 

Collector to Collector Voltage 

100 

‐‐ 

‐‐ 

V 

 

 

DC Current Gain 

‐‐ 

1000 

‐‐ 

 

1000 

‐‐ 

‐‐ 

 

‐‐ 

1000 

‐‐ 

 

Collector Saturation Voltage 

‐‐ 

‐‐ 

0.5 

V 

Emitter Cutoff Current 

‐‐ 

‐‐ 

0.2 

pA 

Collector Cutoff Current 

‐‐ 

‐‐ 

100 

pA 

Output Capacitance 

‐‐ 

‐‐ 

2 

pF 

Collector to Collector Capacitance 

‐‐ 

‐‐ 

2 

pF 

Collector to Collector Leakage Current 

‐‐ 

‐‐ 

0.5 

nA 

Current Gain Bandwidth Product 

100 

‐‐ 

‐‐ 

MHz 

NF 

Narrow Band Noise Figure 

‐‐ 

‐‐ 

3 

dB 

f = 1KHz 

Notes: 

1. Absolute Maximum ratings are limiting values above which serviceability may be impaired

2. The reverse base‐to‐emitter voltage must never exceed 6.2 volts; the reverse base‐to‐emitter current must never exceed 10µA. 

 

 

 

 

LS302

MONOLITHIC DUAL

NPN TRANSISTOR

LS302 Features:

Very high gain

Tight matching

Low Output Capacitance

The LS302 is a monolithic pair of high voltage Super-

Beta NPN transistors mounted in a single P-DIP

package. The monolithic dual chip design reduces

parasitics and gives better performance while ensuring

extremely tight matching.

The 8 Pin P-DIP provides ease of manufacturing, and

the symmetrical pinout prevents improper orientation.

(See Packaging Information).

Linear Systems High Voltage Super-Beta Monolithic Dual NPN

Available Packages:

LS302 in P-DIP

LS302 available as bare die

Please contact Micross for full package and die dimensions:

P-DIP (Top View)