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AD9434

Rev. A | Page 21 of 28

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to clock duty cycle. A 5% tolerance is commonly

required on the clock duty cycle to maintain dynamic performance

characteristics. The AD9434 contains a duty cycle stabilizer (DCS)

that retimes the nonsampling edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows a wide range

of clock input duty cycles without affecting the performance of

the AD9434.

The duty cycle stabilizer uses a delay-locked loop (DLL) to

create the nonsampling edge. As a result, any changes to the

sampling frequency require approximately 5 μs to allow the

DLL to acquire and lock to the new rate.

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency

(fA) due only to aperture jitter (tJ) can be calculated by

SNR Degradation = 20 × log10(1/2 × π × fA × tJ)

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter specifications. IF undersampling

applications are particularly sensitive to jitter (see Figure 48).

Treat the clock input as an analog signal in cases where aperture

jitter may affect the dynamic range of the AD9434. Separate power

supplies for clock drivers from the ADC output driver supplies

to avoid modulating the clock signal with digital noise. Low

jitter, crystal-controlled oscillators make the best clock sources.

If the clock is generated from another type of source (by gating,

dividing, or other methods), it should be retimed by the

original clock at the last step.

Refer to the AN-501 Application Note and the AN-756

Application Note for more in-depth information about jitter

performance as it relates to ADCs (visit www.analog.com).

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1000

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0.125ps

0.25ps

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ANALOG INPUT FREQUENCY (MHz)

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RMS CLOCK JITTER REQUIREMENT

Figure 48. Ideal SNR vs. Input Frequency and Jitter

POWER DISSIPATION AND POWER-DOWN MODE

As shown in Figure 31, the power dissipated by the AD9434 is

proportional to its sample rate. The digital power dissipation

does not vary much because it is determined primarily by the

DRVDD supply and bias current of the LVDS output drivers.

By asserting PDWN (Pin 29) high, the AD9434 is placed in

standby mode or full power-down mode, as determined by the

contents of Serial Port Register 08. Reasserting the PDWN pin

low returns the AD9434 to its normal operational mode.

An additional standby mode is supported by means of varying

the clock input. When the clock rate falls below 50 MHz, the

AD9434 assumes a standby state. In this case, the biasing network

and internal reference remain on, but digital circuitry is powered

down. Upon reactivating the clock, the AD9434 resumes normal

operation after allowing for the pipeline latency.

DIGITAL OUTPUTS

Digital Outputs and Timing

The AD9434 differential outputs conform to the ANSI-644

LVDS standard on default power-up. This can be changed to a

low power, reduced signal option similar to the IEEE 1596.3

standard using the SPI. This LVDS standard can further reduce

the overall power dissipation of the device, which reduces the

power by ~39 mW. See the Memory Map section for more infor-

mation. The LVDS driver current is derived on chip and sets

the output current at each output equal to a nominal 3.5 mA.

A 100 Ω differential termination resistor placed at the LVDS

receiver inputs results in a nominal 350 mV swing at the receiver.

The AD9434 LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs that have LVDS capability

for superior switching performance in noisy environments.

Single point-to-point net topologies are recommended with a

100 Ω termination resistor placed as close to the receiver as

possible. No far end receiver termination or poor differential

trace routing may result in timing errors. It is recommended

that the trace length be no longer than 24 inches and that the

differential output traces be kept close together and at equal

lengths.

An example of the LVDS output using the ANSI standard (default)

data eye and a time interval error (TIE) jitter histogram with

trace lengths less than 24 inches on regular FR-4 material is

shown in Figure 49. Figure 50 shows an example of when the

trace lengths exceed 24 inches on regular FR-4 material. Notice

that the TIE jitter histogram reflects the decrease of the data eye

opening as the edge deviates from the ideal position. It is up to

the user to determine if the waveforms meet the timing budget

of the design when the trace lengths exceed 24 inches.

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