CS1601-FSZ datasheet(10/16 Pages) CIRRUS

10 / 16 page

CS1601

DS931PP6

5.2 Startup vs. Normal Operation Mode

The CS1601 has two discrete operation modes: startup and

normal. Startup mode will be activated when Vlink is less than

90% of nominal value, VO(startup) and remains active until Vlink

reaches 100% of nominal value, as shown in Figure 15.

Startup mode is activated during initial system power-up. Any

Vlink drop to less than VO(startup), such as a load change, can

cause the system to enter startup mode until Vlink is brought

back into regulation.

Figure 15. Startup and Normal Modes

Startup mode is defined as a surge of current delivering

maximum power to the output regardless of the load. During

every active switch cycle, the 'ON' time is calculated to drive a

constant peak current over the entire line cycle. However, the

'OFF' time is calculated based on the DCM/CCM boundary

equation.

5.3 Burst Mode

Burst mode is utilized to improve system efficiency when the

system output power (Po) is <5% of nominal. Burst mode is

implemented by intermittently disabling the PFC over a full

half-line period under light-load conditions, as shown in

Figure 16.

Figure 16. Burst Modes

5.4 Output Power and PFC Boost Inductor

In normal operating mode, the nominal output power is

estimated by the following equation.

where:

rated output power of the system



efficiency of the boost converter (estimated as 100%

by the PFC algorithm)

Vin(min) minimum RMS line voltage measured after the

rectifier and EMI filter. Vin(min) is equal to 90Vrms or

108 Vrms depending on the AC Line Voltage

operating range.

Vlink

nominal PFC output voltage; Vlink = 400V when

Vin(min) =90 Vrms or Vlink = 460 V when

Vin(min) = 108Vrms

fmax

maximum switching frequency; for the CS1601

fmax = 70kHz and the CS1601H fmax = 100kHz

boost inductor specified by rated power requirement



margin factor to guarantee rated output power (Po)

against boost inductor tolerances.

Equation 1 is provided for explanation purposes only. Using

substituted required design values for Vlink and fmax gives the

following equation:

Changing the value for the Vlink voltage is not recommended.

Solving Equation 2 for the PFC boost inductor LB gives the

following equation:

If a value of the boost inductor other than that obtained from

Equation 3 above is used, the total output power capability as

well as the minimum input voltage threshold will differ

according to Equation 2. Note that if the input voltage drops

below 108Vrms and the inductance value is <LB, the link

voltage Vlink will drop below 460V and fall out of regulation.

Figure 17. Relative Effects of Varying Boost Inductance

t[ms]

Vlink

[V]

100%

90%

Normal

Mode

Normal

Mode

Vin

[V]

t [ms]

FET

Vgs

Burst Mode

Active

Vin

[W]

t [ms]

PFC

Disable

Burst Threshold



Vin min





Vlink

Vin min







–

2fmax LB Vlink



---------------------------------------------------------



[Eq.1]



108V





460V

108V





–

270kHz

LB 460V



-------------------------------------------------------------



[Eq.2]



108V





460V

108V





–

270kHz Po

460V



-------------------------------------------------------------



[Eq.3]

VAC(rms)

108

305

L > LB

L = LB

L < LB 

CS1601-FSZ 数据表(PDF) 10 Page - Cirrus Logic

CS1601-FSZ 数据表(HTML) 10 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

数据表下载

链接网址

CS1601-FSZ 数据表(PDF) 10 Page - Cirrus Logic

CS1601-FSZ 数据表(HTML) 10 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

数据表 下载

链接网址

数据表下载