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PCA9560D 数据表(PDF) 12 Page - NXP Semiconductors |
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PCA9560D 数据表(HTML) 12 Page - NXP Semiconductors |
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12 / 17 page  Philips Semiconductors Product data sheet PCA9560 Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch 2004 May 19 12 SAC CHARACTERISTICS SYMBOL PARAMETER LIMITS UNIT SYMBOL PARAMETER MIN. TYP. MAX. UNIT MUX_IN ⇒ MUX_OUT tPLH LOW-to-HIGH transition time — 28 40 ns tPHL HIGH-to-LOW transition time — 8 15 ns Select ⇒ MUX_OUT tPLH LOW-to-HIGH transition time — 30 43 ns tPHL HIGH-to-LOW transition time — 10 15 ns tR Output rise time 1.0 — 3 ns/V tF Output fall time 1.0 — 3 ns/V CL Test load capacitance on outputs — — 50 pF Select ⇒ NON-MUXED_OUT tPLH LOW-to-HIGH transition time — 30 40 ns tPHL HIGH-to-LOW transition time — 9 15 ns AC SPECIFICATIONS SYMBOL PARAMETER STANDARD MODE I2C-BUS FAST MODE I2C-BUS UNITS MIN MAX MIN MAX fSCL Operating frequency 0 100 0 400 kHz tBUF Bus free time between STOP and START conditions 4.7 — 1.3 — µs tHD;STA Hold time after (repeated) START condition 4.0 — 0.6 — µs tSU;STA Repeated START condition setup time 4.7 — 0.6 — µs tSU;STO Set-up time for STOP condition 4.0 — 0.6 — µs tHD;DAT Data in hold time 0 — 0 — ns tVD;ACK Valid time for ACK condition2 0.3 3.45 0.1 0.9 µs tVD;DAT Data out valid time3 300 — 50 — ns tSU;DAT Data set-up time 250 — 100 — ns tLOW Clock LOW period 4.7 — 1.3 — µs tHIGH Clock HIGH period 4.0 — 0.6 — µs tF Clock/Data fall time — 300 20 + 0.1 Cb1 300 ns tR Clock/Data rise time — 1000 20 + 0.1 Cb1 300 ns tSP Pulse width of spikes that must be suppressed by the input filters — 50 — 50 ns NOTES: 1. Cb = total capacitance of one bus line in pF. 2. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. 3. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. |
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