Philips Semiconductors

Product data sheet

PCA9560

Dual 5-bit multiplexed 1-bit latched

2004 May 19

7

(SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may

be initiated only when the bus is not busy.

Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as

changes in the data line at this time will be interpreted as control signals (see Figure 5).

SDA

SCL

SW00363

data line

stable;

data valid

change

of data

allowed

Figure 5. Bit transfer

Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined

as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 6).

System configuration

A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device initiates a transfer is the ‘master’ and the

devices which are controlled by the master are the ‘slaves’ (see Figure 7).

SDA

SCL

SW00365

S

P

SDA

SCL

START condition

STOP condition

Figure 6. Definition of start and stop conditions

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

SW00366

MULTIPLEXER

SLAVE

Figure 7. System configuration