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L6230 数据表(PDF) 13 Page - STMicroelectronics |
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L6230 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 24 page ![]() L6230 Circuit description Doc ID 18094 Rev 2 13/24 5.3 Non-dissipative overcurrent detection and protection The L6230 integrates an overcurrent detection circuit (OCD) for full protection. This circuit provides output-to-output and output-to-ground short circuit protection as well. With this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 10 shows a simplified schematic for the overcurrent detection circuit. To implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current IREF. When the output current reaches the detection threshold (typically ISOVER = 2.8 A) the OCD comparator signals a fault condition. When a fault condition is detected, an internal open drain MOS with a pull down capability of 4 mA connected to pin DIAG is turned on. The pin DIAG-EN can be used to signal the fault condition to a μC and to shut down the three-phase bridge simply by connecting the pin to an external R-C (see REN, CEN). Figure 10. Overcurrent protection simplified schematic Figure 11 shows the overcurrent detection operation. The disable time tDISABLE before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by CEN and REN values and its magnitude is reported in Figure 12. The delay time tDELAY before turning off the bridge when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in Figure 13 CEN is also used for providing immunity to pin DIAG\EN against fast transient noises. Therefore the value of CEN should be chosen as big as possible according to the maximum tolerable delay time and the REN value should be chosen according to the desired disable time. The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 100 kΩ and 5.6 nF that allow obtaining 200 μs disable time. + OVER TEMPERATURE IREF IREF I1+I2 / n I1 / n HIGH SIDE DMOS POWER SENSE 1 cell POWER SENSE 1 cell POWER SENSE 1 cell POWER DMOS n cells POWER DMOS n cells POWER DMOS n cells HIGH SIDE DMOS HIGH SIDE DMOS OUT1 OUT2 VSA OUT3 VSB I1 I2 I3 I2/ n I3/ n OCD COMPARATOR TO GATE LOGIC INTERNAL OPEN-DRAIN RDS(ON) 40 Ω TYP. CEN REN DIAG\EN VDD μC or LOGIC D02IN1381 |
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