MSP430F42xA

MIXED SIGNAL MICROCONTROLLER

SLAS587 -- FEBRUARY 2008

9

POST OFFICE BOX 655303

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

that are not allocated to a functional purpose are not physically present in the device. Simple software access

is provided with this arrangement.

interrupt enable 1 and 2

76

54

0

UTXIE0

OFIE

WDTIE

32

1

rw–0

rw–0

rw–0

Address

0h

URXIE0

ACCVIE

NMIIE

rw–0

rw–0

rw–0

WDTIE:

Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer

is configured in interval timer mode.

OFIE:

Oscillator fault interrupt enable

NMIIE:

Nonmaskable interrupt enable

ACCVIE:

Flash access violation interrupt enable

URXIE0:

USART0: UART and SPI receive-interrupt enable

UTXIE0:

USART0: UART and SPI transmit-interrupt enable

765

4

0

321

Address

1h

BTIE

rw-0

BTIE:

Basic Timer1 interrupt enable

interrupt flag register 1 and 2

76

54

0

UTXIFG0

OFIFG

WDTIFG

32

1

rw–0

rw–1

rw–(0)

Address

02h

URXIFG0

NMIIFG

rw–1

rw–0

WDTIFG:

power up or a reset condition at the RST/NMI pin in reset mode.

OFIFG:

Flag set on oscillator fault

NMIIFG:

Set via RST/NMI pin

URXIFG0:

USART0: UART and SPI receive flag

UTXIFG0:

USART0: UART and SPI transmit flag

765

4

0

321

Address

3h

BTIFG

rw-0

BTIFG:

Basic Timer1 interrupt flag