SYNCHRONOUS PWM CONTROLLER WITH

DUAL LOW DROPOUT REGULATOR

CONTROLLERS

© 2000 SEMTECH CORP.

PRELIMINARY - October 16, 2000

SC1109

13

TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com

LAYOUT GUIDELINES

Careful attention to layout requirements are necessary

for successful implementation of the SC1109 PWM

controller. High currents switching at 200kHz are pre-

sent in the application and their effect on ground plane

voltage differentials must be understood and mini-

mized.

1). The high power parts of the circuit should be laid out

first. A ground plane should be used, the number and

position of ground plane interruptions should be such

as to not unnecessarily compromise ground plane in-

tegrity. Isolated or semi-isolated areas of the ground

plane may be deliberately introduced to constrain

ground currents to particular areas, for example the in-

put capacitor and bottom FET ground.

2). The loop formed by the Input Capacitor(s) (Cin), the

Top FET (Q1) and the Bottom FET (Q2) must be kept

as small as possible. This loop contains all the high cur-

rent, fast transition switching. Connections should be as

wide and as short as possible to minimize loop induc-

tance. Minimizing this loop area will a) reduce EMI, b)

lower ground injection currents, resulting in electrically

“cleaner” grounds for the rest of the system and c) mini-

mize source ringing, resulting in more reliable gate

switching signals.

3). The connection between the junction of Q1, Q2 and

the output inductor should be a wide trace or copper

region. It should be as short as practical. Since this

connection has fast voltage transitions, keeping this

connection short will minimize EMI. Also keep the

Phase connection to the IC short, top FET gate charge

currents flow in this trace.

4) The Output Capacitor(s) (Cout) should be located as

close to the load as possible, fast transient load cur-

Layout diagram for the SC1109

+

2.5V

+

1.8V

3.3V IN

+

C10

330uF

VTT

5V IN

U4

SC1109CS

PWRGD

BCAP-

STBY

PHASE

GND

DH

BST

VOSENSE

SS/EN

BCAP+

VCC

DL

GATE2

GATE1

LDOS1

LDOS2

+

5V STBY

+

12V IN

high current paths.

Heavy Lines indicate