MSP430F449IPZ datasheet(39/79 Pages) TI

39 / 79 page

MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x

MIXED SIGNAL MICROCONTROLLER

SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

Schmitt-trigger inputs − ports P1, P2, P3, P4, P5, P6

PARAMETER

VCC

MIN

TYP

MAX

UNIT

Positive going input threshold voltage

2.2 V

1.1

1.5

VIT+

Positive-going input threshold voltage

3 V

1.5

1.9

Negative going input threshold voltage

2.2 V

0.4

0.9

VIT−

Negative-going input threshold voltage

3 V

0.9

1.3

Input voltage hysteresis (V

)

2.2 V

0.3

1.1

Vhys

Input voltage hysteresis (VIT+ − VIT−)

3 V

0.5

standard inputs − RST/NMI, JTAG (TCK, TMS, TDI/TCLK)

PARAMETER

VCC

MIN

TYP

MAX

UNIT

VIL

Low-level input voltage

22V/3V

VSS

VSS+0.6

VIH

High-level input voltage

2.2 V / 3 V

0.8

×VCC

VCC

inputs Px.x, TAx, TBx

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

P t P1 P2 P1

t P2

l t i

2.2 V/3 V

1.5

cycle

t(int)

External interrupt timing

Port P1, P2: P1.x to P2.x, external trigger signal

for the interrupt flag, (see Note 1)

2.2 V

(int)

for the interrupt flag, (see Note 1)

3 V

Timer A Timer B capture

TA0, TA1, TA2

2.2 V

t(cap)

Timer_A, Timer_B capture

timing

TB0, TB1, TB2, TB3, TB4, TB5, TB6

(see Note 2)

3 V

f(TAext)

Timer_A, Timer_B clock

frequency externally applied

TACLK TBCLK INCLK: t

2.2 V

MHz

f(TBext)

frequency externally applied

to pin

TACLK, TBCLK, INCLK: t(H) = t(L)

3 V

MHz

f(TAint)

Timer_A, Timer_B clock

SMCLK or ACLK signal selected

2.2 V

MHz

f(TBint)

Timer_A, Timer_B clock

frequency

SMCLK or ACLK signal selected

3 V

MHz

NOTES:

1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with

trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in

MCLK cycles.

2. Seven capture/compare registers in ’x44x(1) and three capture/compare registers in ’x43x(1).

leakage current (see Notes 1 and 2)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

Ilkg(P1.x)

Port P1

Port 1: V(P1.x)

±50

Ilkg(P2.x)

Port P2

Port 2: V(P2.x)

±50

Ilkg(P3.x)

Leakage

Port P3

Port 3: V(P3.x)

2 2 V/3 V

±50

Ilkg(P4.x)

Leakage

current

Port P4

Port 4: V(P4.x)

2.2 V/3 V

±50

Ilkg(P5.x)

Port P5

Port 5: V(P5.x)

±50

Ilkg(P6.x)

Port P6

Port 6: V(P6.x)

±50

NOTES:

1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.

2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.

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