Frame1Two-WireSlaveAddressByte

Frame2PointerRegisterByte

1

StartBy

Master

ACKBy

TMP103

ACKBy

TMP103

1

9

1

Frame3DataByte

ACKBy

TMP103

1

D7

SDA

(Continued)

SCL

(Continued)

D6

D5

D4

D3

D2

D1

D0

9

9

SDA

SCL

1

1

0

A2

(1)

A1

(1)

A0

(1)

R/W

0

0

0

0

0

0

P1

P0

¼

¼

StopBy

Master

Frame1Two-WireSlaveAddressByte

Frame2PointerRegisterByte

1

StartBy

Master

ACKBy

TMP103

ACKBy

TMP103

Frame3Two-WireSlaveAddressByte

Frame4DataByteReadRegister

StartBy

Master

ACKBy

TMP103

ACKBy

Master

From

TMP103

1

9

1

9

1

9

1

9

SDA

SCL

1

1

0

R/W

0

0

0

0

0

0

P1

P0

¼

¼

¼

SDA

(Continued)

SCL

(Continued)

1

1

1

0

A2

(1)

A1

(1)

A0

(1)

A2

(1)

A1

(1)

A0

(1)

R/W

D7

D6

D5

D4

D3

D2

D1

D0

StopBy

Master

StopBy

Master

TMP103

www.ti.com

SBOS545A

– FEBRUARY 2011 – REVISED MARCH 2011

(1)

The value of A0, A1, and A2 are determined by the TMP103 version; see Table 9.

Figure 12. Two-Wire Timing Diagram for Write Word Format

(1)

The value of A0, A1, and A2 are determined by the TMP103 version; see Table 9.

Figure 13. Two-Wire Timing Diagram for Read Word Format

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© 2011, Texas Instruments Incorporated

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