SC1152

PROGRAMMABLE SYNCHRONOUS DC/DC

CONTROLLER FOR ADVANCED PROCESSORS

© 1998 SEMTECH CORP.

652 MITCHELL ROAD NEWBURY PARK CA 91320

April 28, 1998

5

NOTE:

(1) All VID codes not specifically listed are invalid and cause shutdown exactly as if the shutdown pin had been

asserted.

OUTPUT VOLTAGE TABLE

Unless specified: V

PARAMETER

CONDITIONS

VID

43210

MIN

TYP

MAX

UNITS

Output Voltage

(1)

I

00101

1.782

1.800

1.818

V

(Figure 1)

00100

1.832

1.850

1.868

00011

1.881

1.900

1.919

00010

1.931

1.950

1.969

00001

1.980

2.000

2.020

00000

2.030

2.050

2.070

11111

1.980

2.000

2.020

11110

2.079

2.100

2.121

11101

2.178

2.200

2.222

11100

2.277

2.300

2.323

11011

2.376

2.400

2.424

11010

2.475

2.500

2.525

11001

2.574

2.600

2.626

11000

2.673

2.700

2.727

10111

2.772

2.800

2.828

10110

2.871

2.900

2.929

10101

2.970

3.000

3.030

10100

3.069

3.100

3.131

10011

3.168

3.200

3.232

10010

3.267

3.300

3.333

10001

3.366

3.400

3.434

10000

3.465

3.500

3.535

THEORY OF OPERATION

The voltage at the V

input of the error amplifier. The non-inverting input of the error amplifier is supplied with a DC voltage derived by

the DAC from the internal trimmed bandgap voltage reference. The output of the error amplifier is compared to

the triangular output of the internal oscillator to generate a fixed frequency, variable duty cycle pulse train. The

internal oscillator uses an on-chip capacitor and precision trimmed current sources to set the frequency to 200

kHz.

The generated pulse train is gated with the output of the current limit latch and the inhibit signal to produce a

drive signal for the upper FET. It is also inverted to produce a drive signal for the lower FET. These FET drive

signals are modified by the “shoot-through control” circuitry so that the top FET turn-on is delayed until the bottom

FET has turned off, and visa-versa.

The current limit latch is set (ending the upper FET drive pulse early) if the current limit comparator indicates an

overcurrent condition. The latch is reset at the start of each oscillator period.

The PWRGOOD and OVP signals are derived from the voltage at the V

internal feedback chain.