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TMS320F2811PBKA 数据表(PDF) 92 Page - Texas Instruments |
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TMS320F2811PBKA 数据表(HTML) 92 Page - Texas Instruments |
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92 / 170 page  TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 SPRS174S – APRIL 2001 – REVISED MARCH 2011 www.ti.com 6.4 Current Consumption Table 6-1. TMS320F281x Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During Low-Power Modes at 150-MHz SYSCLKOUT IDD IDDIO (1) IDD3VFL IDDA (2) MODE TEST CONDITIONS TYP MAX(3) TYP MAX(3) TYP MAX(3) TYP MAX(3) All peripheral clocks are enabled. All PWM pins are toggled at 100 kHz. Data is continuously transmitted out of Operational the SCIA, SCIB, and CAN ports. The 195 mA(4) 230 mA 15 mA 30 mA 40 mA 45 mA 40 mA 50 mA hardware multiplier is exercised. Code is running out of flash with 5 wait-states. • Flash is powered down • XCLKOUT is turned off IDLE 125 mA 150 mA 5 mA 10 mA 2 µA 4 µA 1 µA 20 µA • All peripheral clocks are on, except ADC • Flash is powered down • Peripheral clocks are turned off STANDBY 5 mA 10 mA 5 µA 20 µA 2 µA 4 µA 1 µA 20 µA • Pins without an internal PU/PD are tied high/low • Flash is powered down • Peripheral clocks are turned off HALT 70 µA 5 µA 20 µA 2 µA 4 µA 1 µA 20 µA • Pins without an internal PU/PD are tied high/low • Input clock is disabled (1) IDDIO current is dependent on the electrical loading on the I/O pins. (2) IDDA includes current into VDDA1, VDDA2, AVDDREFBG, and VDDAIO pins. (3) MAX numbers are at 125°C, and MAX voltage (VDD = 1.89 V; VDDIO, VDD3VFL, VDDA = 3.47 V). (4) IDD represents the total current drawn from the 1.8-V rail (VDD). It includes a small amount of current (<1 mA) drawn by VDD1. NOTE HALT and STANDBY modes cannot be used when the PLL is disabled. 92 Electrical Specifications Copyright © 2001–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 |
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