TMS320F2811PBKA datasheet(109/170 Pages) TI

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d(WAKE-STBY)

d(IDLE-XCOH)

32 SYSCLKOUT Cycles

Wake-up

Signal

X1/XCLKIN

XCLKOUT

Flushing Pipeline

Device

Status

STANDBY

Normal Execution

STANDBY

w(WAKE-INT)

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

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SPRS174S – APRIL 2001 – REVISED MARCH 2011

IDLE instruction is executed to put the device into STANDBY mode.

The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below

before being turned off:

•

16 cycles, when DIVSEL = 00 or 01

•

32 cycles, when DIVSEL = 10

•

64 cycles, when DIVSEL = 11

This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in

progress and its access time is longer than this number, then it will fail. It is recommended that STANDBY mode be

entered from SARAM without an XINTF access in progress.

Clocks to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in

STANDBY mode.

The external wake-up signal is driven active.

After a latency period, the STANDBY mode is exited.

Normal execution resumes. The device will respond to the interrupt (if enabled).

Figure 6-16. STANDBY Entry and Exit Timing

Electrical Specifications

109

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TMS320F2811PBKA 数据表(PDF) 109 Page - Texas Instruments

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