SC1406A

© 2000 SEMTECH CORP.

652 MITCHELL ROAD

NEWBURY PARK CA 91320

PORTABLE PENTIUM

POWER SUPPLY CONTROLLER

January 28, 2000

2

Pentium is a registered trademark of Intel Corporation

PIN DESCRIPTION

Pin

Pin Name Pin Function

1

HYS

Core comparator hysteresis settling.

2

CLSET

Current limit setting pin.

3

VCOUT

Voltage clamp output.

4

VCIN

Voltage clamp input.

5

VCBYP

Voltage clamp bypass pin. Needs to have a 1500pF cap from this pin to ground to ensure

proper operation.

6

VID4

VID most significant bit main controller voltage programming DAC input.

7

VID3

VID input

8

VID2

VID input

9

VID1

VID input

10

VID0

VID least significant bit main controller voltage programming DAC input.

11

BASE25

2.5V Linear regulator drive.

12

FB25

2.5V Linear regulator output feedback.

13

BASE15

1.5V Linear regulator drive.

14

FB15

1.5V Linear regulator output feedback.

15

EN

Enable. SC1406A is enabled when this signal is High. This is capable of accepting 5.0V signal

level. When used with the SC1405 driver, this pin can be connected to the PWRDY pin of the

SC1405 to include UVLO feature on the V_5 (Intel Smart Driver’s V

16

PWRGD

Power Good. When the main converter output approaches and stays within ±12% of the VID

DAC setting, and both soft-start circuits periods for the main core controller and linear regulator

controllers have been terminated, this signal is driven high to VCC level. During UVLO, this

signal is undefined.

17

LBIN

Low battery input. This pin is used to set the minimum voltage to the converter through an

external resistor divider. When the input to this pin is less than 1.225V, typical, Tamky is held in

an Under-Voltage-Lock-Out mode regardless of the status of EN.

18

SSLR

Linear regulators soft start. During power-up with EN high and not in UVLO, the external soft

start capacitor (1200pF, typ) is charged by an internal 1µA current source to set the ramp up

time of the linear regulator outputs, 1.5V and 2.5V. This ramp up time is typically 2ms, 6ms

max. This is discharged through an internal switch when BIASEN is low, EN low or enter UVLO

region. Enabling internal bias and soft start requires the pin voltage to drop below a threshold of

150mV typical (200mV max). Linear regulator soft start current tolerance tracks the core soft

start current within 10%.

19

SSCORE

Main controller CORE output soft start. During power-up with EN high and not in UVLO, the

external soft start capacitor (1800pF, typ) is charged by an internal 1µA current source to set

the ramp up time of the main converter output. This ramp up time is typically 3ms, 6ms max.

This is discharged by an internal switch when BIASEN is low, EN pin is low or in UVLO.

Enabling internal bias and soft start requires the pin voltage to drop below a threshold of

150mV typical (200mV max). Core soft start current tolerance tracks the LDO soft start current

to within 10%.