UNISONIC TECHNOLOGIES CO., LTD

UR5595

CMOS IC

www.unisonic.com.tw

1 of 12

Copyright © 2009 Unisonic Technologies Co., Ltd

QW-R502-062.B

DDR TERMINATION

REGULATOR

DESCRIPTION

The UTC UR5595 is a linear bus termination regulator

designed to meet JEDEC SSTL-2 and SSTL-3 (Stub Series

Terminated Logic) specifications for termination of DDR-SDRAM.

The device contains a high-speed operational amplifier to provide

excellent response to the load transients, and can deliver 1.5A

continuous current and transient peaks up to 3A in the application

as required for DDR-SDRAM termination.

the reference for the application of the chipset and DIMMs.

stage has been designed to maintain excellent load regulation and

with fast response time to minimum the transition preventing

shoot-through. The UTC UR5595 also incorporates two distinct

power rails that separates the analog circuitry (AVIN) from the

power output stage (PVIN). This power rail split can be utilized to

reduce the internal power dissipation. And this also permits UTC

UR5595

to provide a termination solution for DDRII SDRAM.

FEATURES

* Power regulating with driving and sinking capability

* Low output voltage offset

* No external resistors required

* Low external component count

* Linear topology

* Low cost and easy to use

* Thermal shutdown protection

Lead-free:

UR5595L

Halogen-free: UR5595G

ORDERING INFORMATION

Ordering Number

Normal

Lead Free

Halogen Free

Package

Packing

UR5595-S08-R

UR5595L-S08-R

UR5595G-S08-R

SOP-8

Tape Reel

UR5595-SH2-R

UR5595L-SH2-R

UR5595G-SH2-R

HSOP-8

Tape Reel