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LTC2635

2635fb

operation

The LTC2635 is a family of quad voltage output DACs in

16-pin QFN and 10-lead MSOP packages. Each DAC can

operate rail-to-rail using an external reference, or with its

full-scale voltage set by an integrated reference. Eighteen

combinations of accuracy (12-, 10-, and 8-bit), power-on

reset value (zero-scale, mid-scale in internal reference

mode, or mid-scale in external reference mode), DAC

power-down output load (high impedance or 200kΩ),

and full-scale voltage (2.5V or 4.096V) are available. The

LTC2635 is controlled using a 2-wire I2C interface.

Power-On Reset

The LTC2635-HZ/-LZ clear the output to zero-scale when

power is first applied, making system initialization con-

sistent and repeatable.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2635

contains circuitry to reduce the power-on glitch: the

analog output typically rises less than 5mV above zero-

scale during power on. In general, the glitch amplitude

decreases as the power supply ramp time is increased.

See “Power-On Reset Glitch” in the Typical Performance

Characteristics section.

The LTC2635-HMI/-LMI/-LMX provide an alternative

reset, setting the output to mid-scale when power is first

applied. The LTC2635-LMI and LTC2635-HMI power

up in internal reference mode, with the output set to a

mid-scale voltage of 1.25V and 2.048V, respectively. The

LTC2635-LMX power-up in external reference mode, with

the output set to mid-scale of the external reference. The

LTC2635-LMO powers up in internal reference mode with

all the DAC channels placed in the high-impedance state

(powered-down). Input and DAC registers are set to the

mid-scale code, and only the internal reference is powered

up, causing supply current to be typically 100µA upon

power up. Default reference mode selection is described

in the Reference Modes section.

Power Supply Sequencing

The voltage at REF (Pin 10 – QFN, Pin 7 – MSOP) must

be kept within the range –0.3V ≤ VREF ≤ VCC + 0.3V (see

Absolute Maximum Ratings). Particular care should be

taken to observe these limits during power supply turn-

on and turn-off sequences, when the voltage at VCC is in

transition.

Transfer Function

The digital-to-analog transfer function is

VOUT(IDEAL) =











 VREF – VREFLO

(

)+ VREFLO

where k is the decimal equivalent of the binary DAC input

code,Nistheresolution,andVREFiseither2.5V(LTC2635-

LMI/-LMX/-LMO/-LZ)or4.096V(LTC2635-HMI/-HZ)when

in Internal Reference mode, and the voltage at REF when

in External Reference mode.

I2C Serial Interface

The LTC2635 communicates with a host using the stan-

dard 2-wire I2C interface. The timing diagrams (Figures

1 and 2) show the timing relationship of the signals on

the bus. The two bus lines, SDA and SCL, must be high

when the bus is not in use. External pull-up resistors or

current sources are required on these lines. The value of

these pull-up resistors is dependent on the power supply

and can be obtained from the I2C specifications. For an I2C

bus operating in the fast mode, an active pull-up will be

necessary if the bus capacitance is greater than 200pF.

The LTC2635 is a receive-only (slave) device. The master

can write to the LTC2635. The LTC2635 will not acknowl-

edge (NAK) a read request from the master.

START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be

high. A bus master signals the beginning of a communica-

tion to a slave device by transmitting a START condition.

A START condition is generated by transitioning SDA from

high to low while SCL is high.

When the master has finished communicating with the

slave, it issues a STOP condition. A STOP condition is

generated by transitioning SDA from low to high while

SCL is high. The bus is then free for communication with

another I2C device.

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