LH28F016LL

16M (1M × 16, 2M × 8) Flash Memory

2

Figure 2. LH28F016LL Block Diagram (Architectural Evolution Includes Page Buffers,

Queue Registers and Extended Status Registers)

OUTPUT

BUFFER

OUTPUT

BUFFER

INPUT

BUFFER

INPUT

BUFFER

ID

REGISTER

OUTPUT

MULTIPLEXER

CSR

ESRs

DATA

COMPARATOR

DATA

QUEUE

REGISTERS

PAGE

BUFFERS

I/O

LOGIC

CUI

WSM

. . .

Y GATING/SENSING

Y-DECODER

X-DECODER

OE

WE

WP

RP

PROGRAM/

ERASE

VOLTAGE

SWITCH

DC/DC

CONVERTER

BYTE

LX

CX

GND

RY/BY

ADDRESS

COUNTER

ADDRESS

QUEUE

LATCHES

INPUT

BUFFER

. . .

28F016LLT-2