Vishay Siliconix

AN821

Document Number 71622

28-Feb-06

www.vishay.com

1

Wharton McDaniel

MOSFETs for switching applications are now available

with die on resistances around 1 m

Ω and with the

capability to handle 85 A. While these die capabilities

represent a major advance over what was available

just a few years ago, it is important for power MOSFET

packaging technology to keep pace. It should be obvi-

ous that degradation of a high performance die by the

package is undesirable. PowerPAK is a new package

technology that addresses these issues. In this appli-

cation note, PowerPAK’s construction is described.

Following this mounting information is presented

including land patterns and soldering profiles for max-

imum reliability. Finally, thermal and electrical perfor-

mance is discussed.

THE PowerPAK PACKAGE

The PowerPAK package was developed around the

SO-8 package (Figure 1). The PowerPAK SO-8 uti-

lizes the same footprint and the same pin-outs as the

standard SO-8. This allows PowerPAK to be substi-

tuted directly for a standard SO-8 package. Being a

leadless package, PowerPAK SO-8 utilizes the entire

SO-8 footprint, freeing space normally occupied by the

leads, and thus allowing it to hold a larger die than a

standard SO-8. In fact, this larger die is slightly larger

than a full sized DPAK die. The bottom of the die attach

pad is exposed for the purpose of providing a direct,

low resistance thermal path to the substrate the device

is mounted on. Finally, the package height is lower

than the standard SO-8, making it an excellent choice

for applications with space constraints.

PowerPAK SO-8 SINGLE MOUNTING

The PowerPAK single is simple to use. The pin

arrangement (drain, source, gate pins) and the pin

dimensions are the same as standard SO-8 devices

(see Figure 2). Therefore, the PowerPAK connection

pads match directly to those of the SO-8. The only dif-

ference is the extended drain connection area. To take

immediate advantage of the PowerPAK SO-8 single

devices, they can be mounted to existing SO-8 land

patterns.

The minimum land pattern recommended to take full

advantage of the PowerPAK thermal performance see

Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Sili-

conix MOSFETs. Click on the PowerPAK SO-8 single

in the index of this document.

In this figure, the drain land pattern is given to make full

contact to the drain pad on the PowerPAK package.

This land pattern can be extended to the left, right, and

top of the drawn pattern. This extension will serve to

increase the heat dissipation by decreasing the ther-

mal resistance from the foot of the PowerPAK to the

PC board and therefore to the ambient. Note that

increasing the drain land area beyond a certain point

will yield little decrease in foot-to-board and foot-to-

ambient thermal resistance. Under specific conditions

of board configuration, copper weight and layer stack,

experiments have found that more than about 0.25 to

land) will yield little improvement in thermal perfor-

mance.

Figure 1. PowerPAK 1212 Devices

Figure 2.

Standard SO-8

PowerPAK SO-8