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18B20 数据表(PDF) 16 Page - Maxim Integrated Products |
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18B20 数据表(HTML) 16 Page - Maxim Integrated Products |
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16 / 22 page ![]() DS18B20 16 of 22 The DS18B20 samples the 1-Wire bus during a window that lasts from 15 µs to 60µs after the master initiates the write time slot. If the bus is high during the sampling window, a 1 is written to the DS18B20. If the line is low, a 0 is written to the DS18B20. Figure 14. Read/Write Time Slot Timing Diagram READ TIME SLOTS The DS18B20 can only transmit data to the master when the master issues read time slots. Therefore, the master must generate read time slots immediately after issuing a Read Scratchpad [BEh] or Read Power Supply [B4h] command, so that the DS18B20 can provide the requested data. In addition, the master can generate read time slots after issuing Convert T [44h] or Recall E 2 [B8h] commands to find out the status of the operation as explained in the DS18B20 Function Commands section. All read time slots must be a minimum of 60 µs in duration with a minimum of a 1µs recovery time between slots. A read time slot is initiated by the master device pulling the 1-Wire bus low for a minimum of 1 µs and then releasing the bus (see Figure 14). After the master initiates the read time slot, the DS18B20 will begin transmitting a 1 or 0 on bus. The DS18B20 transmits a 1 by leaving the bus high and transmits a 0 by pulling the bus low. When transmitting a 0, the DS18B20 will release the bus by the end of the time slot, and the bus will be pulled back to its high idle state by the pullup resister. Output 45 µs 15 µs VPU GND 1-WIRE BUS 60 µs < T X “0” < 120µ s 1 µs < T REC < ∞ DS18B20 Samples MIN TYP MAX 15 µs 30 µs > 1 µs MASTER WRITE “0” SLOT MASTER WRITE “1” SLOT VPU GND 1-WIRE BUS 15 µs MASTER READ “0” SLOT MASTER READ “1” SLOT Master samples Master samples START OF SLOT START OF SLOT > 1 µs 1 µs < T REC < ∞ 15 µs 15 µs 30 µs 15 µs DS18B20 Samples MIN TYP MAX LINE TYPE LEGEND Bus master pulling low DS18B20 pulling low Resistor pullup > 1 µs |
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