FM25640C - 64Kb 5V SPI F-RAM

Rev. 1.1

June 2011

2 of 13

Instruction Decode

Clock Generator

Control Logic

Write Protect

Instruction Register

Address Register

Counter

1,024 x 64

FRAM Array

13

Data I/O Register

8

Nonvolatile Status

Register

3

WP

CS

HOLD

SCK

SO

Figure 1. Block Diagram

Pin Description

Pin Name

I/O

Pin Description

/CS

Input

Chip Select: Enables and disables the device. When /CS is high, the output pin SO is hi-

Z, all other inputs are ignored, and the device remains in a low-power standby mode.

When /CS is low, the part will respond to the SCK signal. A falling edge on /CS must

occur for every op-code.

SCK

Input

Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the

rising edge and outputs occur on the falling edge. The device is static so the clock

frequency may be any value between 0 and 20 MHz and may be interrupted at any time.

/HOLD

Input

Hold: The /HOLD signal is used when the host CPU must interrupt a memory operation

for another task. Asserting the /HOLD signal low pauses the current operation. The

device ignores SCK and /CS. All transitions on /HOLD must occur while SCK is low.

/WP

Input

Write Protect: This pin prevents write operations to the status register. This is critical

since other write protection features are controlled through the status register. A

complete explanation of write protection is provided below. *Note that the function of

/WP is different from the FM25040 where it prevents all writes to the part.

SI

Input

Serial Input: SI is the data input pin. It is sampled on the rising edge of SCK and is

ignored otherwise. It should always be driven to a valid logic level to meet IDD

specifications.

* SI may be connected to SO for a single pin data interface.

SO

Output

Serial Output: SO is the data output pin. It is driven during read cycles and remains hi-Z

at all other times including when HOLD\ is low. Data transitions are driven on the falling

edge of the serial clock.

* SO can be connected to SI for a single pin data interface since the part communicates

in half-duplex.

VDD

Supply

Supply Voltage: 5V

VSS

Supply

Ground