Document Number: 71397

S11-0179-Rev. F, 07-Feb-11

www.vishay.com

9

Vishay Siliconix

DG411L, DG412L, DG413L

SCHEMATIC DIAGRAM (Typical Channel)

TEST CIRCUITS

Figure 1.

Level

Shift/

Drive

S

V+

GND

V-

D

V-

V+

Figure 2. Switching Time

0 V

Logic

Input

Switch

Input*

Switch

Output

3 V

50%

0 V

Switch

Input*

90 %

90 %

Note:

Logic input waveform is inverted for switches that

have the opposite logic sense control

V+

IN

S

D

V-

GND

35 pF

V-

300

Ω

V+

Figure 3. Break-Before-Make (DG413L)

0 V

Logic

Input

Switch

Switch

Output

3 V

50 %

0 V

Output

0 V

90 %

90 %

V+

V-

300

Ω

35 pF

GND

300

Ω

35 pF

V-