HT48R005 datasheet(39/62 Pages) HOLTEK

39 / 62 page

HT48R005/HT46R005

Rev. 1.00

November 29, 2011

A/D Operation

The START bit in the ADCR register is used to start and

reset the A/D converter. When the microcontroller sets

this bit from low to high and then low again, an analog to

digital conversion cycle will be initiated. When the

START bit is brought from low to high but not low again,

the EOCB bit in the ADCR register will be set high and

the analog to digital converter will be reset. It is the

START bit that is used to control the overall start opera-

tion of the internal analog to digital converter.

The EOCB bit in the ADCR register is used to indicate

when the analog to digital conversion process is com-

plete. This bit will be automatically set to "0" by the

microcontroller after a conversion cycle has ended. In

addition, the corresponding A/D interrupt request flag

will be set in the interrupt control register, and if the inter-

rupts are enabled, an appropriate internal interrupt sig-

nal will be generated. This A/D internal interrupt signal

will direct the program flow to the associated A/D inter-

nal interrupt address for processing. If the A/D internal

interrupt is disabled, the microcontroller can be used to

poll the EOCB bit in the ADCR register to check whether

it has been cleared as an alternative method of detect-

ing the end of an A/D conversion cycle.

The ADC module power is managed by the ADONB in

the ACSR register and the PCRn bits in the ADCR regis-

ter. The accompanying table illustrates the power con-

trol for the ADC module. As we can see from this table,

the ADC module can be disabled by setting the PCRn

bits to

²0² or the ADONB bit to ²0².It¢s recommended to

disable the ADC module to reduce power consumption

when the A/D converter function is not being used. Note

that the ADC module ON or OFF will not be affected by

entering the HALT mode.

PCRn

Bits

HALT

Instruction

ADONB

Bit

ADC

On/Off

= 0

Off

> 0

Off

Note: X: Don

¢t care

A/D Converter On/Off Control

The clock source for the A/D converter, which originates

from the system clock fSYS, can be chosen to be either

fSYS or a subdivided version of fSYS .The division ratio

value is determined by the ADCS2~ADCS0 bits in the

ACSR register.

Although the A/D clock source is determined by the sys-

tem clock fSYS, and by bits ADCS2~ADCS0, there are

some limitations on the maximum A/D clock source

speed that can be selected. As the minimum value of per-

missible A/D clock period, tADCK,is0.5

ms, care must be

taken for system clock frequencies equal to or greater

than 4MHz. For example, if the system clock operates at

a frequency of 4MHz, the ADCS2~ADCS0 bits should

not be set to

²100². Doing so will give A/D clock periods

that are less than the minimum A/D clock period which

may result in inaccurate A/D conversion values. Refer to

the following table for examples, where values marked

with an asterisk * show where, depending upon the de-

vice, special care must be taken, as the values may be

less than the specified minimum A/D Clock Period.

· ACSR Register

Bit

76543210

Name

TEST

ADONB

¾¾¾

ADCS2

ADCS1

ADCS0

R/W

¾¾¾

R/W

POR

¾¾¾

000

Bit 7

TEST: for test mode use only

Bit 6

ADONB: ADC module power on/off control bit

0: ADC module power on

1: ADC module power off

Note: 1. it is recommended to set ADONB=1 before entering sleep for saving power.

2. ADONB=1 will power down the ADC module.

Bit 5~3

unimplemented, read as

²0²

Bit 2~0

ADCS2~ADCS0 : Select A/D converter clock source

000: fSYS/2

001: fSYS/8

010: fSYS/32

011: undefined, can

¢t be used.

100: fSYS

101: fSYS/4

110: fSYS/16

111: undefined, can

¢t be used.

These three bits are used to select the clock source for the A/D converter.

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