HT82V42 datasheet(9/24 Pages) HOLTEK

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HT82V42

Rev. 1.20

December 8, 2010

CDS/CIS Processing

For CCD type input signals, the time at which the reset

level is sampled, is adjustable by setting control bits

CDSREF[1:0] as shown in the previous figure.

For CIS type input signals, non-CDS processing is

used. During this case, the video level is processed with

the voltage level on VRLC/VBIAS, the pin VRLC/VBIAS

is generated internally or externally. The VRLC/VBIAS

is sampled by Rs at the same time as Vs samples the

video level in this mode.

PGA Gain Registers

There are three PGA registers which are used to individ-

ually program the gain. Bits D7 through D0 control the

gain range in 256 increments. See the figure for a graph

of the PGA gain versus PGA register code. The coding

for the PGA registers is a straight binary number, with all

zero words corresponding to the minimum gain setting

(0.68x) and all one words corresponding to the maxi-

mum gain setting (8x).

The PGA has a gain range from 0.68x (-3.3dB) to 8x

(18dB), adjustable in 256 steps. The Figure shows the

PGA gain as a function of the PGA register code. Al-

though the gain curve is approximately linear in dB, the

gain in V/V varies in nonlinear proportion with the regis-

ter code, according to the following the equation:

Gain (V/V) = 186 / (278-PGA[7:0])

Gain (dB) = 20LOG10 (186/(278-PGA[7:0]))

Gain(V/V) Gain (dB)

MSB

LSB

00000000

0.68

-3.3

010111001

11000000

2.23

11100000

3.50

10.8

111111118

Note: * Power-on default value

PGA Gain Register Settings

HT82V42 数据表(PDF) 9 Page - Holtek Semiconductor Inc

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