CS5463 datasheet(16/46 Pages) CIRRUS

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CS5463

DS678F3

5. FUNCTIONAL DESCRIPTION

5.1 Analog Inputs

The CS5463 is equipped with two fully differential input

channels. The inputs VIN

 and IIN are designated as

the voltage and current channel inputs, respectively.

The full-scale differential input voltage for the current

and voltage channel is

250 mV

5.1.1 Voltage Channel

The output of the line voltage resistive divider or trans-

former is connected to the VIN+ and VIN- input pins of

the CS5463. The voltage channel is equipped with a

10x fixed-gain amplifier. The full-scale signal level that

can be applied to the voltage channel is

250 mV. If the

input signal is a sine wave the maximum RMS voltage

at a gain 10x is:

which is approximately 70.7% of maximum peak volt-

age. The voltage channel is also equipped with a Volt-

age

Gain

allowing

for

additional

programmable gain of up to 4x.

5.1.2 Current Channel

The output of the current-sense resistor or transformer

is connected to the IIN+ and IIN- input pins of the

CS5463. To accommodate different current sensing el-

ements the current channel incorporates a programma-

ble gain amplifier (PGA) with two programmable input

gains. Configuration Register bit Igain (see Table 1) de-

fines the two gain selections and corresponding maxi-

mum input-signal level.

For example, if Igain=0, the current channel’s PGA gain

is set to 10x. If the input signals are pure sinusoids with

zero phase shift, the maximum peak differential signal

on the current or voltage channel is

250 mV

P. The in-

put signal levels are approximately 70.7% of maximum

peak voltage producing a full-scale energy pulse regis-

tration equal to 50% of absolute maximum energy pulse

registration. This will be discussed further in See Sec-

tion 5.5 Energy Pulse Output on page 17.

The Current Gain Register also facilitates an additional

programmable gain of up to 4x. If an additional gain is

applied to the voltage and/or current channel, the maxi-

mum input range should be adjusted accordingly.

5.2 IIR Filters

The current and voltage channel are equipped with a

4th-order IIR filter, that is used to compensate for the

magnitude roll off of the low-pass decimation filter. Op-

erational Mode Register

bit IIR engages the IIR filters in

both the voltage and current channels.

5.3 High-pass Filters

By removing the offset from either channel, no error

component will be generated at DC when computing the

active power. By removing the offset from both chan-

nels, no error component will be generated at DC when

computing VRMS, IRMS, and apparent power. Operation-

al Mode Register

bits VHPF and IHPF activate the HPF

in the voltage and current channel respectively. When a

high-pass filter is active in only one channel, an all-pass

filter (APF) is applied to the other channel. The APF has

an amplitude response that is flat within the channel

bandwidth and is used for matching phase in systems

where only one HPF is engaged.

5.4 Performing Measurements

The CS5463 performs measurements of instantaneous

voltage (Vn) and current (In), and calculates instanta-

neous power (Pn) at an output word rate (OWR) of

where K is the clock divider selected in the Configura-

tion Register

The RMS voltage (VRMS), RMS current (IRMS), and ac-

tive power (Pactive) are computed using N instantaneous

samples of Vn, In, and Pn respectively, where N is the

value in the Cycle Count Register and is referred to as

a “computation cycle”. The apparent power (S) is the

product of VRMS and IRMS. A computation cycle is de-

rived from the master clock (MCLK), with frequency:

Under default conditions and with K = 1, N = 4000, and

MCLK = 4.096 MHz – the OWR = 4000 Hz and the

ComputationCycle= 1Hz.

All measurements are available as a percentage of full

scale. The format for signed registers is a two’s comple-

ment, normalized value between -1 and +1. The format

Igain

Maximum Input Range

0±250 mV

10x

±50 mV

50x

Table 1. Current Channel PGA Setting

250mV

---------------------

176.78mV

RMS



OWR

MCLK K





1024

-----------------------------

Computation Cycle

OWR

---------------

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