PCF8563 datasheet(17/23 Pages) TGS

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PCF8563

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start-up times experienced by these types of circuits, a mechanism has been built in to

disable the POR and hence speed up on-board test of the device. The setting of this mode

requires that the I 2 C-bus pins, SDA and SCL, be toggled in a specific order as shown in

Figure 5. All timing values are required minimum.

Once the override mode has been entered, the chip immediately stops being reset and

normal operation starts i.e. entry into the EXT_CLK test mode via I 2 C-bus access. The

override mode is cleared by writing a logic 0 to bit TESTC. Re-entry into the override mode

is only possible after TESTC is set to logic 1. Setting TESTC to logic 0 during normal

operation has no effect except to prevent entry into the POR override mode.

POR override sequence

Serial interface

The serial interface of the

PCF8563 is the I 2 C-bus. A detailed description of the I 2 C-bus

specification, including applications, is given in the brochure: The I 2 C-bus and how to use

it, order no. 9398 393 40011 or I 2 C Peripherals Data Handbook IC12.

Characteristics of the I

2 C-bus

The I 2 C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy.

The I 2 C-bus system configuration is shown in Figure below. A device generating a message

is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls

the message is the ‘master’ and the devices which are controlled by the master are the

‘slaves’.

I 2 C-bus system configuration

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